| Message ID | 1533584470-10334-1-git-send-email-manasi.d.navare@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3] drm/i915/dp: Configure Display stream splitter registers during DSC enable | expand |
>-----Original Message----- >From: Navare, Manasi D >Sent: Monday, August 6, 2018 12:41 PM >To: intel-gfx@lists.freedesktop.org >Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Jani Nikula ><jani.nikula@linux.intel.com>; Ville Syrjala <ville.syrjala@linux.intel.com>; >Srivatsa, Anusha <anusha.srivatsa@intel.com> >Subject: [PATCH v3] drm/i915/dp: Configure Display stream splitter registers >during DSC enable > >Display Stream Splitter registers need to be programmed to enable the joiner if >two DSC engines are used and also to enable the left and the right DSC engines. >This happens as part of the DSC enabling routine in the source in atomic commit. > >v2: >* Rebase (Manasi) This is v2 of the patch correct? No functional changes since the v1...only rebase. I got confused with the patch prefix. But the patch itself looks good, assuming this is the latest version: Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intelcom> >Cc: Jani Nikula <jani.nikula@linux.intel.com> >Cc: Ville Syrjala <ville.syrjala@linux.intel.com> >Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> >Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> >--- > drivers/gpu/drm/i915/intel_vdsc.c | 21 +++++++++++++++++++++ > 1 file changed, 21 insertions(+) > >diff --git a/drivers/gpu/drm/i915/intel_vdsc.c >b/drivers/gpu/drm/i915/intel_vdsc.c >index 098f9b6..10e38396 100644 >--- a/drivers/gpu/drm/i915/intel_vdsc.c >+++ b/drivers/gpu/drm/i915/intel_vdsc.c >@@ -1011,6 +1011,11 @@ void intel_dsc_enable(struct intel_encoder *encoder, >{ > struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); >+ enum pipe pipe = crtc->pipe; >+ i915_reg_t dss_ctl1_reg, dss_ctl2_reg; >+ u32 dss_ctl1_val = 0; >+ u32 dss_ctl2_val = 0; > > if (!crtc_state->dsc_params.compression_enable) > return; >@@ -1024,5 +1029,21 @@ void intel_dsc_enable(struct intel_encoder *encoder, > > intel_dp_send_dsc_pps_sdp(encoder, crtc_state); > >+ /* Configure DSS_CTL registers for DSC */ >+ if (encoder->type == INTEL_OUTPUT_EDP) { >+ dss_ctl1_reg = DSS_CTL1; >+ dss_ctl2_reg = DSS_CTL2; >+ } else { >+ dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe); >+ dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); >+ } >+ dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; >+ if (crtc_state->dsc_params.dsc_split) { >+ dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; >+ dss_ctl1_val |= JOINER_ENABLE; >+ } >+ I915_WRITE(dss_ctl1_reg, dss_ctl1_val); >+ I915_WRITE(dss_ctl2_reg, dss_ctl2_val); >+ > return; > } >-- >2.7.4
diff --git a/drivers/gpu/drm/i915/intel_vdsc.c b/drivers/gpu/drm/i915/intel_vdsc.c index 098f9b6..10e38396 100644 --- a/drivers/gpu/drm/i915/intel_vdsc.c +++ b/drivers/gpu/drm/i915/intel_vdsc.c @@ -1011,6 +1011,11 @@ void intel_dsc_enable(struct intel_encoder *encoder, { struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + enum pipe pipe = crtc->pipe; + i915_reg_t dss_ctl1_reg, dss_ctl2_reg; + u32 dss_ctl1_val = 0; + u32 dss_ctl2_val = 0; if (!crtc_state->dsc_params.compression_enable) return; @@ -1024,5 +1029,21 @@ void intel_dsc_enable(struct intel_encoder *encoder, intel_dp_send_dsc_pps_sdp(encoder, crtc_state); + /* Configure DSS_CTL registers for DSC */ + if (encoder->type == INTEL_OUTPUT_EDP) { + dss_ctl1_reg = DSS_CTL1; + dss_ctl2_reg = DSS_CTL2; + } else { + dss_ctl1_reg = ICL_PIPE_DSS_CTL1(pipe); + dss_ctl2_reg = ICL_PIPE_DSS_CTL2(pipe); + } + dss_ctl2_val |= LEFT_BRANCH_VDSC_ENABLE; + if (crtc_state->dsc_params.dsc_split) { + dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; + dss_ctl1_val |= JOINER_ENABLE; + } + I915_WRITE(dss_ctl1_reg, dss_ctl1_val); + I915_WRITE(dss_ctl2_reg, dss_ctl2_val); + return; }
Display Stream Splitter registers need to be programmed to enable the joiner if two DSC engines are used and also to enable the left and the right DSC engines. This happens as part of the DSC enabling routine in the source in atomic commit. v2: * Rebase (Manasi) Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Ville Syrjala <ville.syrjala@linux.intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> --- drivers/gpu/drm/i915/intel_vdsc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)