diff mbox series

clk: renesas: r8a77980: add CMT clocks

Message ID 32394fbc-1b10-5708-2769-38cc2eff5042@cogentembedded.com (mailing list archive)
State Awaiting Upstream, archived
Headers show
Series clk: renesas: r8a77980: add CMT clocks | expand

Commit Message

Sergei Shtylyov Sept. 1, 2018, 6:54 p.m. UTC 
Now that RCLK has been added by Geert, we can add the CMT module clocks.

Based on the original (and large) patch by Vladimir Barinov.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

---
This patch is against the 'clk-renesas' branch of Geert's 'renesas-drivers.git'
repo.

 drivers/clk/renesas/r8a77980-cpg-mssr.c |    4 ++++
 1 file changed, 4 insertions(+)

Comments

Geert Uytterhoeven Sept. 3, 2018, 7:48 a.m. UTC | #1 
On Sat, Sep 1, 2018 at 8:54 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Now that RCLK has been added by Geert, we can add the CMT module clocks.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in clk-renesas-for-v4.20 with s/add/Add/.

Gr{oetje,eeting}s,

                        Geert
diff mbox series

Patch

Index: renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c
===================================================================
--- renesas-drivers.orig/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ renesas-drivers/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -119,6 +119,10 @@  static const struct mssr_mod_clk r8a7798
 	DEF_MOD("msiof0",		 211,	R8A77980_CLK_MSO),
 	DEF_MOD("sys-dmac2",		 217,	R8A77980_CLK_S0D3),
 	DEF_MOD("sys-dmac1",		 218,	R8A77980_CLK_S0D3),
+	DEF_MOD("cmt3",			 300,	R8A77980_CLK_R),
+	DEF_MOD("cmt2",			 301,	R8A77980_CLK_R),
+	DEF_MOD("cmt1",			 302,	R8A77980_CLK_R),
+	DEF_MOD("cmt0",			 303,	R8A77980_CLK_R),
 	DEF_MOD("tpu0",			 304,	R8A77980_CLK_S3D4),
 	DEF_MOD("sdif",			 314,	R8A77980_CLK_SD0),
 	DEF_MOD("pciec0",		 319,	R8A77980_CLK_S2D2),