| Message ID | 20180820134013.16527-1-icenowy@aosc.io (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks | expand |
On Mon, Aug 20, 2018 at 09:40:13PM +0800, Icenowy Zheng wrote: > On the H6, the MMC module clocks are fixed in the new timing mode, > i.e. they do not have a bit to select the mode. These clocks have > a 2x divider somewhere between the clock and the MMC module. > > To be consistent with other SoCs supporting the new timing mode, > we model the 2x divider as a fixed post-divider on the MMC module > clocks. > > This patch adds the post-dividers to the MMC clocks, following the > approach on A64. > > Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU") > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Thanks! Maxime
Quoting Icenowy Zheng (2018-08-20 06:40:13) > On the H6, the MMC module clocks are fixed in the new timing mode, > i.e. they do not have a bit to select the mode. These clocks have > a 2x divider somewhere between the clock and the MMC module. > > To be consistent with other SoCs supporting the new timing mode, > we model the 2x divider as a fixed post-divider on the MMC module > clocks. > > This patch adds the post-dividers to the MMC clocks, following the > approach on A64. > > Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU") This commit doesn't exist. Did you mean: 524353ea48 instead?
于 2018年8月28日 GMT+08:00 上午4:23:54, Stephen Boyd <sboyd@kernel.org> 写到: >Quoting Icenowy Zheng (2018-08-20 06:40:13) >> On the H6, the MMC module clocks are fixed in the new timing mode, >> i.e. they do not have a bit to select the mode. These clocks have >> a 2x divider somewhere between the clock and the MMC module. >> >> To be consistent with other SoCs supporting the new timing mode, >> we model the 2x divider as a fixed post-divider on the MMC module >> clocks. >> >> This patch adds the post-dividers to the MMC clocks, following the >> approach on A64. >> >> Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 >CCU") > >This commit doesn't exist. Did you mean: > >524353ea48 > >instead? Yes, it is. Thanks! > >_______________________________________________ >linux-arm-kernel mailing list >linux-arm-kernel@lists.infradead.org >http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
On Mon, Aug 27, 2018 at 01:23:54PM -0700, Stephen Boyd wrote: > Quoting Icenowy Zheng (2018-08-20 06:40:13) > > On the H6, the MMC module clocks are fixed in the new timing mode, > > i.e. they do not have a bit to select the mode. These clocks have > > a 2x divider somewhere between the clock and the MMC module. > > > > To be consistent with other SoCs supporting the new timing mode, > > we model the 2x divider as a fixed post-divider on the MMC module > > clocks. > > > > This patch adds the post-dividers to the MMC clocks, following the > > approach on A64. > > > > Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU") > > This commit doesn't exist. Did you mean: > > 524353ea48 > > instead? I changed it. Please also use 12-characters commit IDs, as recommended in the kernel documentation. Maxime
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c index bdbfe78fe133..3d60f7978506 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c @@ -408,26 +408,29 @@ static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0); static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x", "pll-periph1-2x" }; -static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc_parents, 0x830, - 0, 4, /* M */ - 8, 2, /* N */ - 24, 3, /* mux */ - BIT(31),/* gate */ - 0); - -static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc_parents, 0x834, - 0, 4, /* M */ - 8, 2, /* N */ - 24, 3, /* mux */ - BIT(31),/* gate */ - 0); - -static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc_parents, 0x838, - 0, 4, /* M */ - 8, 2, /* N */ - 24, 3, /* mux */ - BIT(31),/* gate */ - 0); +static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830, + 0, 4, /* M */ + 8, 2, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 2, /* post-div */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834, + 0, 4, /* M */ + 8, 2, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 2, /* post-div */ + 0); + +static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838, + 0, 4, /* M */ + 8, 2, /* N */ + 24, 3, /* mux */ + BIT(31), /* gate */ + 2, /* post-div */ + 0); static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0); static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
On the H6, the MMC module clocks are fixed in the new timing mode, i.e. they do not have a bit to select the mode. These clocks have a 2x divider somewhere between the clock and the MMC module. To be consistent with other SoCs supporting the new timing mode, we model the 2x divider as a fixed post-divider on the MMC module clocks. This patch adds the post-dividers to the MMC clocks, following the approach on A64. Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by: Icenowy Zheng <icenowy@aosc.io> --- drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 43 +++++++++++++++------------- 1 file changed, 23 insertions(+), 20 deletions(-)