| Message ID | 1536589634-29680-1-git-send-email-raviraj.p.sitaram@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1] drm/i915/chv: Update csc coefficient matrix during modeset | expand |
On Mon, Sep 10, 2018 at 07:57:14PM +0530, raviraj.p.sitaram@intel.com wrote: > From: P Raviraj Sitaram <raviraj.p.sitaram@intel.com> > > During modeset, previously configured csc coefficient matrix,if any, will > not persist. This can result in blank screen as csc mode will be programmed > while loading LUT but csc coefficient matrix remains unprogrammed. > > Changes since V1: > - Removed platform check > > Signed-off-by: P Raviraj Sitaram <raviraj.p.sitaram@intel.com> Thanks for the patch. Pushed to dinq. > --- > drivers/gpu/drm/i915/intel_display.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index b2bab57cd113..2b77d9350a3a 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -6014,6 +6014,8 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, > > i9xx_set_pipeconf(intel_crtc); > > + intel_color_set_csc(&pipe_config->base); > + > intel_crtc->active = true; > > intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b2bab57cd113..2b77d9350a3a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -6014,6 +6014,8 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, i9xx_set_pipeconf(intel_crtc); + intel_color_set_csc(&pipe_config->base); + intel_crtc->active = true; intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);