| Message ID | 20180921150351.20898-2-yu-cheng.yu@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Control Flow Enforcement: Shadow Stack | expand |
On Fri, Sep 21, 2018 at 08:03:25AM -0700, Yu-cheng Yu wrote: > diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c > index 772c219b6889..63cbb4d9938e 100644 > --- a/arch/x86/kernel/cpu/scattered.c > +++ b/arch/x86/kernel/cpu/scattered.c > @@ -21,6 +21,7 @@ struct cpuid_bit { > static const struct cpuid_bit cpuid_bits[] = { > { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 }, > { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 }, > + { X86_FEATURE_IBT, CPUID_EDX, 20, 0x00000007, 0}, ^^ missing white space at the end there. > { X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 }, > { X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 }, > { X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 }, > -- > 2.17.1 >
On Tue, 2018-09-25 at 18:27 +0200, Peter Zijlstra wrote: > On Fri, Sep 21, 2018 at 08:03:25AM -0700, Yu-cheng Yu wrote: > > > diff --git a/arch/x86/kernel/cpu/scattered.c > > b/arch/x86/kernel/cpu/scattered.c > > index 772c219b6889..63cbb4d9938e 100644 > > --- a/arch/x86/kernel/cpu/scattered.c > > +++ b/arch/x86/kernel/cpu/scattered.c > > @@ -21,6 +21,7 @@ struct cpuid_bit { > > static const struct cpuid_bit cpuid_bits[] = { > > { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 }, > > { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 }, > > + { X86_FEATURE_IBT, CPUID_EDX, 20, 0x00000007, 0}, > > ^^ > missing white space at the end there. I will fix it. Thanks!
On Fri, Sep 21, 2018 at 08:03:25AM -0700, Yu-cheng Yu wrote: > Add CPUIDs for Control-flow Enforcement Technology (CET). > > CPUID.(EAX=7,ECX=0):ECX[bit 7] Shadow stack > CPUID.(EAX=7,ECX=0):EDX[bit 20] Indirect branch tracking > > Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com> > --- > arch/x86/include/asm/cpufeatures.h | 2 ++ > arch/x86/kernel/cpu/scattered.c | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > index 89a048c2faec..fa69651a017e 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -221,6 +221,7 @@ > #define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */ > #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */ > #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */ > +#define X86_FEATURE_IBT ( 7*32+31) /* Indirect Branch Tracking */ > > /* Virtualization flags: Linux defined, word 8 */ > #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ > @@ -321,6 +322,7 @@ > #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ > #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ > #define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */ > +#define X86_FEATURE_SHSTK (16*32+ 7) /* Shadow Stack */ > #define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */ > #define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */ > #define X86_FEATURE_VPCLMULQDQ (16*32+10) /* Carry-Less Multiplication Double Quadword */ > diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c > index 772c219b6889..63cbb4d9938e 100644 > --- a/arch/x86/kernel/cpu/scattered.c > +++ b/arch/x86/kernel/cpu/scattered.c > @@ -21,6 +21,7 @@ struct cpuid_bit { > static const struct cpuid_bit cpuid_bits[] = { > { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 }, > { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 }, > + { X86_FEATURE_IBT, CPUID_EDX, 20, 0x00000007, 0}, If you haven't noticed, there's already a separate leaf: /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ in arch/x86/include/asm/cpufeatures.h
On Fri, 2018-09-28 at 18:51 +0200, Borislav Petkov wrote: > On Fri, Sep 21, 2018 at 08:03:25AM -0700, Yu-cheng Yu wrote: > > Add CPUIDs for Control-flow Enforcement Technology (CET). > > > > CPUID.(EAX=7,ECX=0):ECX[bit 7] Shadow stack > > CPUID.(EAX=7,ECX=0):EDX[bit 20] Indirect branch tracking > > > > Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com> > > --- > > arch/x86/include/asm/cpufeatures.h | 2 ++ > > arch/x86/kernel/cpu/scattered.c | 1 + > > 2 files changed, 3 insertions(+) > > > > diff --git a/arch/x86/include/asm/cpufeatures.h > > b/arch/x86/include/asm/cpufeatures.h > > index 89a048c2faec..fa69651a017e 100644 > > --- a/arch/x86/include/asm/cpufeatures.h > > +++ b/arch/x86/include/asm/cpufeatures.h > > @@ -221,6 +221,7 @@ > > #define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD > > family 0x17 (Zen) */ > > #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF > > workaround PTE inversion */ > > #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */ > > +#define X86_FEATURE_IBT ( 7*32+31) /* Indirect > > Branch Tracking */ > > > > /* Virtualization flags: Linux defined, word 8 */ > > #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR > > Shadow */ > > @@ -321,6 +322,7 @@ > > #define X86_FEATURE_PKU (16*32+ 3) /* Protection > > Keys for Userspace */ > > #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys > > Enable */ > > #define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 > > Vector Bit Manipulation Instructions */ > > +#define X86_FEATURE_SHSTK (16*32+ 7) /* Shadow Stack */ > > #define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New > > Instructions */ > > #define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */ > > #define X86_FEATURE_VPCLMULQDQ (16*32+10) /* Carry-Less > > Multiplication Double Quadword */ > > diff --git a/arch/x86/kernel/cpu/scattered.c > > b/arch/x86/kernel/cpu/scattered.c > > index 772c219b6889..63cbb4d9938e 100644 > > --- a/arch/x86/kernel/cpu/scattered.c > > +++ b/arch/x86/kernel/cpu/scattered.c > > @@ -21,6 +21,7 @@ struct cpuid_bit { > > static const struct cpuid_bit cpuid_bits[] = { > > { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 }, > > { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 }, > > + { X86_FEATURE_IBT, CPUID_EDX, 20, 0x00000007, 0}, > > If you haven't noticed, there's already a separate leaf: > > /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */ > > in arch/x86/include/asm/cpufeatures.h > I will change to that one. Thanks! Yu-cheng
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 89a048c2faec..fa69651a017e 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -221,6 +221,7 @@ #define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */ #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */ #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */ +#define X86_FEATURE_IBT ( 7*32+31) /* Indirect Branch Tracking */ /* Virtualization flags: Linux defined, word 8 */ #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ @@ -321,6 +322,7 @@ #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ #define X86_FEATURE_AVX512_VBMI2 (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */ +#define X86_FEATURE_SHSTK (16*32+ 7) /* Shadow Stack */ #define X86_FEATURE_GFNI (16*32+ 8) /* Galois Field New Instructions */ #define X86_FEATURE_VAES (16*32+ 9) /* Vector AES */ #define X86_FEATURE_VPCLMULQDQ (16*32+10) /* Carry-Less Multiplication Double Quadword */ diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 772c219b6889..63cbb4d9938e 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -21,6 +21,7 @@ struct cpuid_bit { static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 }, { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 }, + { X86_FEATURE_IBT, CPUID_EDX, 20, 0x00000007, 0}, { X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 }, { X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 }, { X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 },
Add CPUIDs for Control-flow Enforcement Technology (CET). CPUID.(EAX=7,ECX=0):ECX[bit 7] Shadow stack CPUID.(EAX=7,ECX=0):EDX[bit 20] Indirect branch tracking Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com> --- arch/x86/include/asm/cpufeatures.h | 2 ++ arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 3 insertions(+)