@@ -39,6 +39,7 @@
# Argument sets:
&branch imm rs2 rs1
+&arith_imm imm rs1 rd
&shift shamt rs1 rd
&atomic aq rl rs2 rs1 rd
@@ -48,7 +49,7 @@
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
@r ....... ..... ..... ... ..... ....... %rs2 %rs1 %rd
-@i ............ ..... ... ..... ....... imm=%imm_i %rs1 %rd
+@i ............ ..... ... ..... ....... &arith_imm imm=%imm_i %rs1 %rd
@b ....... ..... ..... ... ..... ....... &branch imm=%imm_b %rs2 %rs1
@s ....... ..... ..... ... ..... ....... imm=%imm_s %rs2 %rs1
@u .................... ..... ....... imm=%imm_u %rd
@@ -235,37 +235,50 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a, uint32_t insn)
static bool trans_addi(DisasContext *ctx, arg_addi *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_ADDI, a->rd, a->rs1, a->imm);
- return true;
+ return trans_arith_imm(ctx, a, &tcg_gen_add_tl);
}
static bool trans_slti(DisasContext *ctx, arg_slti *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_SLTI, a->rd, a->rs1, a->imm);
+ TCGv source1;
+ source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, a->imm);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
return true;
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_SLTIU, a->rd, a->rs1, a->imm);
+ TCGv source1;
+ source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, a->imm);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
return true;
}
static bool trans_xori(DisasContext *ctx, arg_xori *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_XORI, a->rd, a->rs1, a->imm);
- return true;
+ return trans_arith_imm(ctx, a, &tcg_gen_xor_tl);
}
+
static bool trans_ori(DisasContext *ctx, arg_ori *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_ORI, a->rd, a->rs1, a->imm);
- return true;
+ return trans_arith_imm(ctx, a, &tcg_gen_or_tl);
}
+
static bool trans_andi(DisasContext *ctx, arg_andi *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_ANDI, a->rd, a->rs1, a->imm);
- return true;
+ return trans_arith_imm(ctx, a, &tcg_gen_and_tl);
}
+
static bool trans_slli(DisasContext *ctx, arg_slli *a, uint32_t insn)
{
if (a->rd != 0) {
@@ -370,13 +383,26 @@ static bool trans_and(DisasContext *ctx, arg_and *a, uint32_t insn)
static bool trans_addiw(DisasContext *ctx, arg_addiw *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_ADDIW, a->rd, a->rs1, a->imm);
- return true;
+#ifdef TARGET_RISCV64
+ bool res = trans_arith_imm(ctx, a, &tcg_gen_add_tl);
+ tcg_gen_ext32s_tl(cpu_gpr[a->rd], cpu_gpr[a->rd]);
+ return res;
+#else
+ return false;
+#endif
}
static bool trans_slliw(DisasContext *ctx, arg_slliw *a, uint32_t insn)
{
- gen_arith_imm(ctx, OPC_RISC_SLLIW, a->rd, a->rs1, a->shamt);
+ TCGv source1;
+ source1 = tcg_temp_new();
+ gen_get_gpr(source1, a->rs1);
+
+ tcg_gen_shli_tl(source1, source1, a->shamt);
+ tcg_gen_ext32s_tl(source1, source1);
+ gen_set_gpr(a->rd, source1);
+
+ tcg_temp_free(source1);
return true;
}
@@ -373,86 +373,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1,
tcg_temp_free(source2);
}
-static void gen_arith_imm(DisasContext *ctx, uint32_t opc, int rd,
- int rs1, target_long imm)
-{
- TCGv source1 = tcg_temp_new();
- int shift_len = TARGET_LONG_BITS;
- int shift_a;
-
- gen_get_gpr(source1, rs1);
-
- switch (opc) {
- case OPC_RISC_ADDI:
-#if defined(TARGET_RISCV64)
- case OPC_RISC_ADDIW:
-#endif
- tcg_gen_addi_tl(source1, source1, imm);
- break;
- case OPC_RISC_SLTI:
- tcg_gen_setcondi_tl(TCG_COND_LT, source1, source1, imm);
- break;
- case OPC_RISC_SLTIU:
- tcg_gen_setcondi_tl(TCG_COND_LTU, source1, source1, imm);
- break;
- case OPC_RISC_XORI:
- tcg_gen_xori_tl(source1, source1, imm);
- break;
- case OPC_RISC_ORI:
- tcg_gen_ori_tl(source1, source1, imm);
- break;
- case OPC_RISC_ANDI:
- tcg_gen_andi_tl(source1, source1, imm);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SLLIW:
- shift_len = 32;
- /* FALLTHRU */
-#endif
- case OPC_RISC_SLLI:
- if (imm >= shift_len) {
- goto do_illegal;
- }
- tcg_gen_shli_tl(source1, source1, imm);
- break;
-#if defined(TARGET_RISCV64)
- case OPC_RISC_SHIFT_RIGHT_IW:
- shift_len = 32;
- /* FALLTHRU */
-#endif
- case OPC_RISC_SHIFT_RIGHT_I:
- /* differentiate on IMM */
- shift_a = imm & 0x400;
- imm &= 0x3ff;
- if (imm >= shift_len) {
- goto do_illegal;
- }
- if (imm != 0) {
- if (shift_a) {
- /* SRAI[W] */
- tcg_gen_sextract_tl(source1, source1, imm, shift_len - imm);
- } else {
- /* SRLI[W] */
- tcg_gen_extract_tl(source1, source1, imm, shift_len - imm);
- }
- /* No further sign-extension needed for W instructions. */
- opc &= ~0x8;
- }
- break;
- default:
- do_illegal:
- gen_exception_illegal(ctx);
- return;
- }
-
- if (opc & 0x8) { /* sign-extend for W instructions */
- tcg_gen_ext32s_tl(source1, source1);
- }
-
- gen_set_gpr(rd, source1);
- tcg_temp_free(source1);
-}
-
static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
target_ulong imm)
{
@@ -534,6 +454,25 @@ static int64_t ex_rvc_register(int reg)
bool decode_insn32(DisasContext *ctx, uint32_t insn);
/* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c"
+
+static bool trans_arith_imm(DisasContext *ctx, arg_arith_imm *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv source1, source2;
+ source1 = tcg_temp_new();
+ source2 = tcg_temp_new();
+
+ gen_get_gpr(source1, a->rs1);
+ tcg_gen_movi_tl(source2, a->imm);
+
+ (*func)(source1, source1, source2);
+
+ gen_set_gpr(a->rd, source1);
+ tcg_temp_free(source1);
+ tcg_temp_free(source2);
+ return true;
+}
+
/* Include insn module translation function */
#include "insn_trans/trans_rvi.inc.c"
#include "insn_trans/trans_rvm.inc.c"