| Message ID | 20181025072349.15173-3-jiada_wang@mentor.com (mailing list archive) |
|---|---|
| State | Under Review |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add AVB Counter Clock | expand |
On Thu, Oct 25, 2018 at 04:23:47PM +0900, jiada_wang@mentor.com wrote: > From: Jiada Wang <jiada_wang@mentor.com> > > Add device tree bindings for avb counter clock for Renesas > R-Car Socs. > > Signed-off-by: Jiada Wang <jiada_wang@mentor.com> > --- > .../bindings/clock/renesas,avb-clk.txt | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/renesas,avb-clk.txt > > diff --git a/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt b/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt > new file mode 100644 > index 000000000000..03bf50b5830c > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt > @@ -0,0 +1,19 @@ > +* Renesas AVB Counter Clock > + > +The AVB Counter Clocks are provided by avb_counter8 Clock Generator, > +avb_counter8 has dividers which operates with S0D1ϕ clock and has > +8 output clocks. > + > +Required Properties: > + - compatible: Must be "renesas,clk-avb" Should be SoC specific? If the h/w block is called "AVB Counter" then use "avb-counter" in the compatible string. > + - reg: Base address and length of the memory resource used by the AVB > + - #clock-cells: Must be 1 > + > +Example > +------- > + > + clk_avb: avb-clock@ec5a011c { clock-controller@... > + compatible = "renesas,clk-avb"; > + reg = <0 0xec5a011c 0 0x24>; > + #clock-cells = <1>; > + }; > -- > 2.17.0 >
Hi Rob On 2018/10/26 6:49, Rob Herring wrote: > On Thu, Oct 25, 2018 at 04:23:47PM +0900, jiada_wang@mentor.com wrote: >> From: Jiada Wang <jiada_wang@mentor.com> >> >> Add device tree bindings for avb counter clock for Renesas >> R-Car Socs. >> >> Signed-off-by: Jiada Wang <jiada_wang@mentor.com> >> --- >> .../bindings/clock/renesas,avb-clk.txt | 19 +++++++++++++++++++ >> 1 file changed, 19 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/renesas,avb-clk.txt >> >> diff --git a/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt b/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt >> new file mode 100644 >> index 000000000000..03bf50b5830c >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt >> @@ -0,0 +1,19 @@ >> +* Renesas AVB Counter Clock >> + >> +The AVB Counter Clocks are provided by avb_counter8 Clock Generator, >> +avb_counter8 has dividers which operates with S0D1ϕ clock and has >> +8 output clocks. >> + >> +Required Properties: >> + - compatible: Must be "renesas,clk-avb" > Should be SoC specific? yes, avb counter clock is SoC specific, I will move avb clock node to Soc .dtsi in next version > > If the h/w block is called "AVB Counter" then use "avb-counter" in the > compatible string. will update compatible string >> + - reg: Base address and length of the memory resource used by the AVB >> + - #clock-cells: Must be 1 >> + >> +Example >> +------- >> + >> + clk_avb: avb-clock@ec5a011c { > clock-controller@... will replace with "clock-controller" Thanks, Jiada > >> + compatible = "renesas,clk-avb"; >> + reg = <0 0xec5a011c 0 0x24>; >> + #clock-cells = <1>; >> + }; >> -- >> 2.17.0 >>
On Thu, Oct 25, 2018 at 9:32 PM Jiada Wang <jiada_wang@mentor.com> wrote: > > Hi Rob > > > On 2018/10/26 6:49, Rob Herring wrote: > > On Thu, Oct 25, 2018 at 04:23:47PM +0900, jiada_wang@mentor.com wrote: > >> From: Jiada Wang <jiada_wang@mentor.com> > >> > >> Add device tree bindings for avb counter clock for Renesas > >> R-Car Socs. > >> > >> Signed-off-by: Jiada Wang <jiada_wang@mentor.com> > >> --- > >> .../bindings/clock/renesas,avb-clk.txt | 19 +++++++++++++++++++ > >> 1 file changed, 19 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/clock/renesas,avb-clk.txt > >> > >> diff --git a/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt b/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt > >> new file mode 100644 > >> index 000000000000..03bf50b5830c > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt > >> @@ -0,0 +1,19 @@ > >> +* Renesas AVB Counter Clock > >> + > >> +The AVB Counter Clocks are provided by avb_counter8 Clock Generator, > >> +avb_counter8 has dividers which operates with S0D1ϕ clock and has > >> +8 output clocks. > >> + > >> +Required Properties: > >> + - compatible: Must be "renesas,clk-avb" > > Should be SoC specific? > yes, avb counter clock is SoC specific, I will move avb clock node to > Soc .dtsi in next version The compatible string should be SoC specific too then. Rob
Quoting jiada_wang@mentor.com (2018-10-25 00:23:47) > From: Jiada Wang <jiada_wang@mentor.com> > > Add device tree bindings for avb counter clock for Renesas > R-Car Socs. > > Signed-off-by: Jiada Wang <jiada_wang@mentor.com> > --- > .../bindings/clock/renesas,avb-clk.txt | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/renesas,avb-clk.txt > > diff --git a/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt b/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt > new file mode 100644 > index 000000000000..03bf50b5830c > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt > @@ -0,0 +1,19 @@ > +* Renesas AVB Counter Clock > + > +The AVB Counter Clocks are provided by avb_counter8 Clock Generator, > +avb_counter8 has dividers which operates with S0D1ϕ clock and has > +8 output clocks. > + > +Required Properties: > + - compatible: Must be "renesas,clk-avb" > + - reg: Base address and length of the memory resource used by the AVB > + - #clock-cells: Must be 1 > + > +Example > +------- > + > + clk_avb: avb-clock@ec5a011c { > + compatible = "renesas,clk-avb"; > + reg = <0 0xec5a011c 0 0x24>; This is an odd register offset. Is this just one clk inside of a larger clk controller?
Hi Stephen Thanks for your comments On 2018/10/30 3:29, Stephen Boyd wrote: > Quoting jiada_wang@mentor.com (2018-10-25 00:23:47) >> From: Jiada Wang <jiada_wang@mentor.com> >> >> Add device tree bindings for avb counter clock for Renesas >> R-Car Socs. >> >> Signed-off-by: Jiada Wang <jiada_wang@mentor.com> >> --- >> .../bindings/clock/renesas,avb-clk.txt | 19 +++++++++++++++++++ >> 1 file changed, 19 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/clock/renesas,avb-clk.txt >> >> diff --git a/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt b/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt >> new file mode 100644 >> index 000000000000..03bf50b5830c >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt >> @@ -0,0 +1,19 @@ >> +* Renesas AVB Counter Clock >> + >> +The AVB Counter Clocks are provided by avb_counter8 Clock Generator, >> +avb_counter8 has dividers which operates with S0D1ϕ clock and has >> +8 output clocks. >> + >> +Required Properties: >> + - compatible: Must be "renesas,clk-avb" >> + - reg: Base address and length of the memory resource used by the AVB >> + - #clock-cells: Must be 1 >> + >> +Example >> +------- >> + >> + clk_avb: avb-clock@ec5a011c { >> + compatible = "renesas,clk-avb"; >> + reg = <0 0xec5a011c 0 0x24>; > This is an odd register offset. Is this just one clk inside of a larger > clk controller? > Yes, avb_counter clock is part of Audio Clock Generator reg: <0 0xec5a0000 0 0x140>, but "adg" has already been declared in R-Car GEN2/GEN3 SoC .dtsi file, with reg: <0 0xec5a0000 0 0x100>, which leaves <0 0xec5a0100 0 0x140> currently not used by any module. Thanks, Jiada
Quoting Jiada Wang (2018-10-31 05:00:49) > On 2018/10/30 3:29, Stephen Boyd wrote: > > Quoting jiada_wang@mentor.com (2018-10-25 00:23:47) > >> +Required Properties: > >> + - compatible: Must be "renesas,clk-avb" > >> + - reg: Base address and length of the memory resource used by the AVB > >> + - #clock-cells: Must be 1 > >> + > >> +Example > >> +------- > >> + > >> + clk_avb: avb-clock@ec5a011c { > >> + compatible = "renesas,clk-avb"; > >> + reg = <0 0xec5a011c 0 0x24>; > > This is an odd register offset. Is this just one clk inside of a larger > > clk controller? > > > Yes, avb_counter clock is part of Audio Clock Generator reg: <0 > 0xec5a0000 0 0x140>, > but "adg" has already been declared in R-Car GEN2/GEN3 SoC .dtsi file, > with reg: <0 0xec5a0000 0 0x100>, > which leaves <0 0xec5a0100 0 0x140> currently not used by any module. > So why can't we expand the register size in the dts file and update the audio clock generator driver to register this avb clock too? Presumably the mapping is large enough to cover the clk registers already so it is more of a formality to expand the register size than a requirement.
Hi Stephen On 2018/11/04 12:14, Stephen Boyd wrote: > Quoting Jiada Wang (2018-10-31 05:00:49) >> On 2018/10/30 3:29, Stephen Boyd wrote: >>> Quoting jiada_wang@mentor.com (2018-10-25 00:23:47) >>>> +Required Properties: >>>> + - compatible: Must be "renesas,clk-avb" >>>> + - reg: Base address and length of the memory resource used by the AVB >>>> + - #clock-cells: Must be 1 >>>> + >>>> +Example >>>> +------- >>>> + >>>> + clk_avb: avb-clock@ec5a011c { >>>> + compatible = "renesas,clk-avb"; >>>> + reg = <0 0xec5a011c 0 0x24>; >>> This is an odd register offset. Is this just one clk inside of a larger >>> clk controller? >>> >> Yes, avb_counter clock is part of Audio Clock Generator reg: <0 >> 0xec5a0000 0 0x140>, >> but "adg" has already been declared in R-Car GEN2/GEN3 SoC .dtsi file, >> with reg: <0 0xec5a0000 0 0x100>, >> which leaves <0 0xec5a0100 0 0x140> currently not used by any module. >> > So why can't we expand the register size in the dts file and update the > audio clock generator driver to register this avb clock too? Presumably > the mapping is large enough to cover the clk registers already so it is > more of a formality to expand the register size than a requirement. I am working on ver2 to expend register size to cover <0 0xec5a0100 0 0x140> in audio clock generator (ADG) driver, but as provider of newly added "AVB_COUNTER" clock, ADG driver also uses these clocks if necessary, so it keeps itself BUSY, and cause ADG driver can't be unloaded. my question is, is such use case allowed? (clock provider is also client of clocks). Thanks, Jiada
Quoting Jiada Wang (2018-11-21 23:06:10) > On 2018/11/04 12:14, Stephen Boyd wrote: > > Quoting Jiada Wang (2018-10-31 05:00:49) > >> On 2018/10/30 3:29, Stephen Boyd wrote: > >>> Quoting jiada_wang@mentor.com (2018-10-25 00:23:47) > >>>> +Required Properties: > >>>> + - compatible: Must be "renesas,clk-avb" > >>>> + - reg: Base address and length of the memory resource used by the AVB > >>>> + - #clock-cells: Must be 1 > >>>> + > >>>> +Example > >>>> +------- > >>>> + > >>>> + clk_avb: avb-clock@ec5a011c { > >>>> + compatible = "renesas,clk-avb"; > >>>> + reg = <0 0xec5a011c 0 0x24>; > >>> This is an odd register offset. Is this just one clk inside of a larger > >>> clk controller? > >>> > >> Yes, avb_counter clock is part of Audio Clock Generator reg: <0 > >> 0xec5a0000 0 0x140>, > >> but "adg" has already been declared in R-Car GEN2/GEN3 SoC .dtsi file, > >> with reg: <0 0xec5a0000 0 0x100>, > >> which leaves <0 0xec5a0100 0 0x140> currently not used by any module. > >> > > So why can't we expand the register size in the dts file and update the > > audio clock generator driver to register this avb clock too? Presumably > > the mapping is large enough to cover the clk registers already so it is > > more of a formality to expand the register size than a requirement. > I am working on ver2 to expend register size to cover <0 0xec5a0100 0 0x140> > in audio clock generator (ADG) driver, but as provider of newly added > "AVB_COUNTER" clock, > ADG driver also uses these clocks if necessary, so it keeps itself BUSY, > and cause ADG driver can't be unloaded. > my question is, is such use case allowed? (clock provider is also client > of clocks). Yes, a clock provider can also be a client of clocks.
diff --git a/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt b/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt new file mode 100644 index 000000000000..03bf50b5830c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,avb-clk.txt @@ -0,0 +1,19 @@ +* Renesas AVB Counter Clock + +The AVB Counter Clocks are provided by avb_counter8 Clock Generator, +avb_counter8 has dividers which operates with S0D1ϕ clock and has +8 output clocks. + +Required Properties: + - compatible: Must be "renesas,clk-avb" + - reg: Base address and length of the memory resource used by the AVB + - #clock-cells: Must be 1 + +Example +------- + + clk_avb: avb-clock@ec5a011c { + compatible = "renesas,clk-avb"; + reg = <0 0xec5a011c 0 0x24>; + #clock-cells = <1>; + };