| Message ID | 20181025144644.15464-44-cota@braap.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [RFC,v4,01/71] cpu: convert queued work to a QSIMPLEQ | expand |
Emilio G. Cota <cota@braap.org> writes: > Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> > Signed-off-by: Emilio G. Cota <cota@braap.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > target/cris/cpu.c | 2 +- > target/cris/helper.c | 6 +++--- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target/cris/cpu.c b/target/cris/cpu.c > index a23aba2688..3cdba581e6 100644 > --- a/target/cris/cpu.c > +++ b/target/cris/cpu.c > @@ -37,7 +37,7 @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value) > > static bool cris_cpu_has_work(CPUState *cs) > { > - return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); > + return cpu_interrupt_request(cs) & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); > } > > /* CPUClass::reset() */ > diff --git a/target/cris/helper.c b/target/cris/helper.c > index d2ec349191..e3fa19363f 100644 > --- a/target/cris/helper.c > +++ b/target/cris/helper.c > @@ -116,7 +116,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, > if (r > 0) { > qemu_log_mask(CPU_LOG_MMU, > "%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x" > - " pc=%x\n", __func__, r, cs->interrupt_request, address, > + " pc=%x\n", __func__, r, cpu_interrupt_request(cs), address, > res.phy, res.bf_vec, env->pc); > } > return r; > @@ -130,7 +130,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) > > D_LOG("exception index=%d interrupt_req=%d\n", > cs->exception_index, > - cs->interrupt_request); > + cpu_interrupt_request(cs)); > > if (env->dslot) { > /* CRISv10 never takes interrupts while in a delay-slot. */ > @@ -192,7 +192,7 @@ void cris_cpu_do_interrupt(CPUState *cs) > > D_LOG("exception index=%d interrupt_req=%d\n", > cs->exception_index, > - cs->interrupt_request); > + cpu_interrupt_request(cs)); > > switch (cs->exception_index) { > case EXCP_BREAK: -- Alex Bennée
diff --git a/target/cris/cpu.c b/target/cris/cpu.c index a23aba2688..3cdba581e6 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -37,7 +37,7 @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value) static bool cris_cpu_has_work(CPUState *cs) { - return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); + return cpu_interrupt_request(cs) & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } /* CPUClass::reset() */ diff --git a/target/cris/helper.c b/target/cris/helper.c index d2ec349191..e3fa19363f 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -116,7 +116,7 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw, if (r > 0) { qemu_log_mask(CPU_LOG_MMU, "%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x" - " pc=%x\n", __func__, r, cs->interrupt_request, address, + " pc=%x\n", __func__, r, cpu_interrupt_request(cs), address, res.phy, res.bf_vec, env->pc); } return r; @@ -130,7 +130,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) D_LOG("exception index=%d interrupt_req=%d\n", cs->exception_index, - cs->interrupt_request); + cpu_interrupt_request(cs)); if (env->dslot) { /* CRISv10 never takes interrupts while in a delay-slot. */ @@ -192,7 +192,7 @@ void cris_cpu_do_interrupt(CPUState *cs) D_LOG("exception index=%d interrupt_req=%d\n", cs->exception_index, - cs->interrupt_request); + cpu_interrupt_request(cs)); switch (cs->exception_index) { case EXCP_BREAK: