| Message ID | 20181102231320.29164-3-jarkko.sakkinen@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Intel SGX1 | expand |
On Sat, Nov 03, 2018 at 01:11:01AM +0200, Jarkko Sakkinen wrote: > From: Kai Huang <kai.huang@linux.intel.com> > > X86_FEATURE_SGX reflects whether or not the CPU supports Intel's > Software Guard eXtensions (SGX). > > Signed-off-by: Kai Huang <kai.huang@linux.intel.com> This and all the other patches of which you're not the author, need to have your SOB after the author's SOB. See Documentation/process/submitting-patches.rst
On Sat, Nov 03, 2018 at 12:33:01AM +0100, Borislav Petkov wrote: > On Sat, Nov 03, 2018 at 01:11:01AM +0200, Jarkko Sakkinen wrote: > > From: Kai Huang <kai.huang@linux.intel.com> > > > > X86_FEATURE_SGX reflects whether or not the CPU supports Intel's > > Software Guard eXtensions (SGX). > > > > Signed-off-by: Kai Huang <kai.huang@linux.intel.com> > > This and all the other patches of which you're not the author, need to > have your SOB after the author's SOB. > > See Documentation/process/submitting-patches.rst Right. I know this but forgot to go through this step. /Jarkko
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 89a048c2faec..22271752fd1e 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -236,6 +236,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */ #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/ #define X86_FEATURE_TSC_ADJUST ( 9*32+ 1) /* TSC adjustment MSR 0x3B */ +#define X86_FEATURE_SGX ( 9*32+ 2) /* Software Guard Extensions */ #define X86_FEATURE_BMI1 ( 9*32+ 3) /* 1st group bit manipulation extensions */ #define X86_FEATURE_HLE ( 9*32+ 4) /* Hardware Lock Elision */ #define X86_FEATURE_AVX2 ( 9*32+ 5) /* AVX2 instructions */