diff mbox series

[PATCH/RFT] pinctrl: sh-pfc: r8a77990: Add HSCIF pins, groups, and functions

Message ID 1540071055-27181-1-git-send-email-ykaneko0929@gmail.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series [PATCH/RFT] pinctrl: sh-pfc: r8a77990: Add HSCIF pins, groups, and functions | expand

Commit Message

Yoshihiro Kaneko Oct. 20, 2018, 9:30 p.m. UTC 
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>

This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to
the R8A77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
---

This patch is based on the sh-pfc branch of Geert Uytterhoeven's
renesas-drivers tree.

 drivers/pinctrl/sh-pfc/pfc-r8a77990.c | 366 ++++++++++++++++++++++++++++++++++
 1 file changed, 366 insertions(+)

Comments

Geert Uytterhoeven Nov. 5, 2018, 3:30 p.m. UTC | #1 
Hi Kaneko-san,

On Sat, Oct 20, 2018 at 11:31 PM Yoshihiro Kaneko <ykaneko0929@gmail.com> wrote:
> From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
>
> This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to
> the R8A77990 SoC.
>
> Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>

Thanks for your patch!

> --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c

> +static const unsigned int hscif3_data_d_pins[] = {
> +       /* RX, TX */
> +       RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 0),

These two pins are exchanged.
According to the datasheet, it should be:

        RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3),

> +};
> +
> +static const unsigned int hscif3_data_d_mux[] = {
> +       HRX3_D_MARK, HTX3_D_MARK,
> +};

> @@ -2454,6 +2738,37 @@ enum {
>                 SH_PFC_PIN_GROUP(du_disp_cde),
>                 SH_PFC_PIN_GROUP(du_cde),
>                 SH_PFC_PIN_GROUP(du_disp),
> +               SH_PFC_PIN_GROUP(hscif0_data_a),
> +               SH_PFC_PIN_GROUP(hscif0_clk_a),
> +               SH_PFC_PIN_GROUP(hscif0_ctrl_a),
> +               SH_PFC_PIN_GROUP(hscif0_data_b),
> +               SH_PFC_PIN_GROUP(hscif0_clk_b),
> +               SH_PFC_PIN_GROUP(hscif1_data_a),
> +               SH_PFC_PIN_GROUP(hscif1_clk_a),
> +               SH_PFC_PIN_GROUP(hscif1_data_b),
> +               SH_PFC_PIN_GROUP(hscif1_clk_b),
> +               SH_PFC_PIN_GROUP(hscif1_ctrl_b),
> +               SH_PFC_PIN_GROUP(hscif2_data_a),
> +               SH_PFC_PIN_GROUP(hscif2_clk_a),
> +               SH_PFC_PIN_GROUP(hscif2_ctrl_a),
> +               SH_PFC_PIN_GROUP(hscif2_data_b),
> +               SH_PFC_PIN_GROUP(hscif3_data_a),
> +               SH_PFC_PIN_GROUP(hscif3_data_b),
> +               SH_PFC_PIN_GROUP(hscif3_clk_b),
> +               SH_PFC_PIN_GROUP(hscif3_data_c),
> +               SH_PFC_PIN_GROUP(hscif3_clk_c),
> +               SH_PFC_PIN_GROUP(hscif3_ctrl_c),
> +               SH_PFC_PIN_GROUP(hscif3_data_d),
> +               SH_PFC_PIN_GROUP(hscif3_data_e),
> +               SH_PFC_PIN_GROUP(hscif3_ctrl_e),
> +               SH_PFC_PIN_GROUP(hscif4_data_a),
> +               SH_PFC_PIN_GROUP(hscif4_clk_a),
> +               SH_PFC_PIN_GROUP(hscif4_ctrl_a),
> +               SH_PFC_PIN_GROUP(hscif4_data_b),
> +               SH_PFC_PIN_GROUP(hscif4_clk_b),
> +               SH_PFC_PIN_GROUP(hscif4_data_c),
> +               SH_PFC_PIN_GROUP(hscif4_data_d),
> +               SH_PFC_PIN_GROUP(hscif4_data_e),
>                 SH_PFC_PIN_GROUP(i2c1_a),
>                 SH_PFC_PIN_GROUP(i2c1_b),
>                 SH_PFC_PIN_GROUP(i2c1_c),

The above doesn't compile, as you forgot to update the size of the
pinmux_groups.common[] array.

> @@ -2781,6 +3142,11 @@ enum {
>         .common = {
>                 SH_PFC_FUNCTION(avb),
>                 SH_PFC_FUNCTION(du),
> +               SH_PFC_FUNCTION(hscif0),
> +               SH_PFC_FUNCTION(hscif1),
> +               SH_PFC_FUNCTION(hscif2),
> +               SH_PFC_FUNCTION(hscif3),
> +               SH_PFC_FUNCTION(hscif4),
>                 SH_PFC_FUNCTION(i2c1),
>                 SH_PFC_FUNCTION(i2c2),
>                 SH_PFC_FUNCTION(i2c4),

The above doesn't compile, as you forgot to update the size of the
pinmux_functions.common[] array.

Gr{oetje,eeting}s,

                        Geert
Yoshihiro Kaneko Nov. 15, 2018, 4:28 p.m. UTC | #2 
Hi Geert-san,

Thanks for your review!!

2018年11月6日(火) 0:30 Geert Uytterhoeven <geert@linux-m68k.org>:
>
> Hi Kaneko-san,
>
> On Sat, Oct 20, 2018 at 11:31 PM Yoshihiro Kaneko <ykaneko0929@gmail.com> wrote:
> > From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> >
> > This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to
> > the R8A77990 SoC.
> >
> > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
> > Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
>
> Thanks for your patch!
>
> > --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
> > +++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
>
> > +static const unsigned int hscif3_data_d_pins[] = {
> > +       /* RX, TX */
> > +       RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 0),
>
> These two pins are exchanged.
> According to the datasheet, it should be:
>
>         RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3),

I will fix it in v2.

>
> > +};
> > +
> > +static const unsigned int hscif3_data_d_mux[] = {
> > +       HRX3_D_MARK, HTX3_D_MARK,
> > +};
>
> > @@ -2454,6 +2738,37 @@ enum {
> >                 SH_PFC_PIN_GROUP(du_disp_cde),
> >                 SH_PFC_PIN_GROUP(du_cde),
> >                 SH_PFC_PIN_GROUP(du_disp),
> > +               SH_PFC_PIN_GROUP(hscif0_data_a),
> > +               SH_PFC_PIN_GROUP(hscif0_clk_a),
> > +               SH_PFC_PIN_GROUP(hscif0_ctrl_a),
> > +               SH_PFC_PIN_GROUP(hscif0_data_b),
> > +               SH_PFC_PIN_GROUP(hscif0_clk_b),
> > +               SH_PFC_PIN_GROUP(hscif1_data_a),
> > +               SH_PFC_PIN_GROUP(hscif1_clk_a),
> > +               SH_PFC_PIN_GROUP(hscif1_data_b),
> > +               SH_PFC_PIN_GROUP(hscif1_clk_b),
> > +               SH_PFC_PIN_GROUP(hscif1_ctrl_b),
> > +               SH_PFC_PIN_GROUP(hscif2_data_a),
> > +               SH_PFC_PIN_GROUP(hscif2_clk_a),
> > +               SH_PFC_PIN_GROUP(hscif2_ctrl_a),
> > +               SH_PFC_PIN_GROUP(hscif2_data_b),
> > +               SH_PFC_PIN_GROUP(hscif3_data_a),
> > +               SH_PFC_PIN_GROUP(hscif3_data_b),
> > +               SH_PFC_PIN_GROUP(hscif3_clk_b),
> > +               SH_PFC_PIN_GROUP(hscif3_data_c),
> > +               SH_PFC_PIN_GROUP(hscif3_clk_c),
> > +               SH_PFC_PIN_GROUP(hscif3_ctrl_c),
> > +               SH_PFC_PIN_GROUP(hscif3_data_d),
> > +               SH_PFC_PIN_GROUP(hscif3_data_e),
> > +               SH_PFC_PIN_GROUP(hscif3_ctrl_e),
> > +               SH_PFC_PIN_GROUP(hscif4_data_a),
> > +               SH_PFC_PIN_GROUP(hscif4_clk_a),
> > +               SH_PFC_PIN_GROUP(hscif4_ctrl_a),
> > +               SH_PFC_PIN_GROUP(hscif4_data_b),
> > +               SH_PFC_PIN_GROUP(hscif4_clk_b),
> > +               SH_PFC_PIN_GROUP(hscif4_data_c),
> > +               SH_PFC_PIN_GROUP(hscif4_data_d),
> > +               SH_PFC_PIN_GROUP(hscif4_data_e),
> >                 SH_PFC_PIN_GROUP(i2c1_a),
> >                 SH_PFC_PIN_GROUP(i2c1_b),
> >                 SH_PFC_PIN_GROUP(i2c1_c),
>
> The above doesn't compile, as you forgot to update the size of the
> pinmux_groups.common[] array.

I will fix it.

>
> > @@ -2781,6 +3142,11 @@ enum {
> >         .common = {
> >                 SH_PFC_FUNCTION(avb),
> >                 SH_PFC_FUNCTION(du),
> > +               SH_PFC_FUNCTION(hscif0),
> > +               SH_PFC_FUNCTION(hscif1),
> > +               SH_PFC_FUNCTION(hscif2),
> > +               SH_PFC_FUNCTION(hscif3),
> > +               SH_PFC_FUNCTION(hscif4),
> >                 SH_PFC_FUNCTION(i2c1),
> >                 SH_PFC_FUNCTION(i2c2),
> >                 SH_PFC_FUNCTION(i2c4),
>
> The above doesn't compile, as you forgot to update the size of the
> pinmux_functions.common[] array.

I will fix it.


Best regards,
Kaneko

>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds
diff mbox series

Patch

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
index 1fdafa4..0d0153a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a77990.c
@@ -1459,6 +1459,290 @@  enum {
 	DU_DISP_MARK,
 };
 
+/* - HSCIF0 --------------------------------------------------*/
+static const unsigned int hscif0_data_a_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
+};
+
+static const unsigned int hscif0_data_a_mux[] = {
+	HRX0_A_MARK, HTX0_A_MARK,
+};
+
+static const unsigned int hscif0_clk_a_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(5, 7),
+};
+
+static const unsigned int hscif0_clk_a_mux[] = {
+	HSCK0_A_MARK,
+};
+
+static const unsigned int hscif0_ctrl_a_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
+};
+
+static const unsigned int hscif0_ctrl_a_mux[] = {
+	HRTS0_N_A_MARK, HCTS0_N_A_MARK,
+};
+
+static const unsigned int hscif0_data_b_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
+};
+
+static const unsigned int hscif0_data_b_mux[] = {
+	HRX0_B_MARK, HTX0_B_MARK,
+};
+
+static const unsigned int hscif0_clk_b_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(6, 13),
+};
+
+static const unsigned int hscif0_clk_b_mux[] = {
+	HSCK0_B_MARK,
+};
+
+/* - HSCIF1 ------------------------------------------------- */
+static const unsigned int hscif1_data_a_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
+};
+
+static const unsigned int hscif1_data_a_mux[] = {
+	HRX1_A_MARK, HTX1_A_MARK,
+};
+
+static const unsigned int hscif1_clk_a_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(5, 0),
+};
+
+static const unsigned int hscif1_clk_a_mux[] = {
+	HSCK1_A_MARK,
+};
+
+static const unsigned int hscif1_data_b_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
+};
+
+static const unsigned int hscif1_data_b_mux[] = {
+	HRX1_B_MARK, HTX1_B_MARK,
+};
+
+static const unsigned int hscif1_clk_b_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(3, 0),
+};
+
+static const unsigned int hscif1_clk_b_mux[] = {
+	HSCK1_B_MARK,
+};
+
+static const unsigned int hscif1_ctrl_b_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
+};
+
+static const unsigned int hscif1_ctrl_b_mux[] = {
+	HRTS1_N_B_MARK, HCTS1_N_B_MARK,
+};
+
+/* - HSCIF2 ------------------------------------------------- */
+static const unsigned int hscif2_data_a_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
+};
+
+static const unsigned int hscif2_data_a_mux[] = {
+	HRX2_A_MARK, HTX2_A_MARK,
+};
+
+static const unsigned int hscif2_clk_a_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(6, 14),
+};
+
+static const unsigned int hscif2_clk_a_mux[] = {
+	HSCK2_A_MARK,
+};
+
+static const unsigned int hscif2_ctrl_a_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
+};
+
+static const unsigned int hscif2_ctrl_a_mux[] = {
+	HRTS2_N_A_MARK, HCTS2_N_A_MARK,
+};
+
+static const unsigned int hscif2_data_b_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+
+static const unsigned int hscif2_data_b_mux[] = {
+	HRX2_B_MARK, HTX2_B_MARK,
+};
+
+/* - HSCIF3 ------------------------------------------------*/
+static const unsigned int hscif3_data_a_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+
+static const unsigned int hscif3_data_a_mux[] = {
+	HRX3_A_MARK, HTX3_A_MARK,
+};
+
+static const unsigned int hscif3_data_b_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
+};
+
+static const unsigned int hscif3_data_b_mux[] = {
+	HRX3_B_MARK, HTX3_B_MARK,
+};
+
+static const unsigned int hscif3_clk_b_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(0, 4),
+};
+
+static const unsigned int hscif3_clk_b_mux[] = {
+	HSCK3_B_MARK,
+};
+
+static const unsigned int hscif3_data_c_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9),
+};
+
+static const unsigned int hscif3_data_c_mux[] = {
+	HRX3_C_MARK, HTX3_C_MARK,
+};
+
+static const unsigned int hscif3_clk_c_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(2, 11),
+};
+
+static const unsigned int hscif3_clk_c_mux[] = {
+	HSCK3_C_MARK,
+};
+
+static const unsigned int hscif3_ctrl_c_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
+};
+
+static const unsigned int hscif3_ctrl_c_mux[] = {
+	HRTS3_N_C_MARK, HCTS3_N_C_MARK,
+};
+
+static const unsigned int hscif3_data_d_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 0),
+};
+
+static const unsigned int hscif3_data_d_mux[] = {
+	HRX3_D_MARK, HTX3_D_MARK,
+};
+
+static const unsigned int hscif3_data_e_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+};
+
+static const unsigned int hscif3_data_e_mux[] = {
+	HRX3_E_MARK, HTX3_E_MARK,
+};
+
+static const unsigned int hscif3_ctrl_e_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8),
+};
+
+static const unsigned int hscif3_ctrl_e_mux[] = {
+	HRTS3_N_E_MARK, HCTS3_N_E_MARK,
+};
+
+/* - HSCIF4 -------------------------------------------------- */
+static const unsigned int hscif4_data_a_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
+};
+
+static const unsigned int hscif4_data_a_mux[] = {
+	HRX4_A_MARK, HTX4_A_MARK,
+};
+
+static const unsigned int hscif4_clk_a_pins[] = {
+	/* SCK */
+	RCAR_GP_PIN(2, 0),
+};
+
+static const unsigned int hscif4_clk_a_mux[] = {
+	HSCK4_A_MARK,
+};
+
+static const unsigned int hscif4_ctrl_a_pins[] = {
+	/* RTS, CTS */
+	RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
+};
+
+static const unsigned int hscif4_ctrl_a_mux[] = {
+	HRTS4_N_A_MARK, HCTS4_N_A_MARK,
+};
+
+static const unsigned int hscif4_data_b_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
+};
+
+static const unsigned int hscif4_data_b_mux[] = {
+	HRX4_B_MARK, HTX4_B_MARK,
+};
+
+static const unsigned int hscif4_clk_b_pins[] = {
+/* SCK */
+	RCAR_GP_PIN(2, 6),
+};
+
+static const unsigned int hscif4_clk_b_mux[] = {
+	HSCK4_B_MARK,
+};
+
+static const unsigned int hscif4_data_c_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
+};
+
+static const unsigned int hscif4_data_c_mux[] = {
+	HRX4_C_MARK, HTX4_C_MARK,
+};
+
+static const unsigned int hscif4_data_d_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
+};
+
+static const unsigned int hscif4_data_d_mux[] = {
+	HRX4_D_MARK, HTX4_D_MARK,
+};
+
+static const unsigned int hscif4_data_e_pins[] = {
+	/* RX, TX */
+	RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
+};
+
+static const unsigned int hscif4_data_e_mux[] = {
+	HRX4_E_MARK, HTX4_E_MARK,
+};
+
 /* - I2C -------------------------------------------------------------------- */
 static const unsigned int i2c1_a_pins[] = {
 	/* SCL, SDA */
@@ -2454,6 +2738,37 @@  enum {
 		SH_PFC_PIN_GROUP(du_disp_cde),
 		SH_PFC_PIN_GROUP(du_cde),
 		SH_PFC_PIN_GROUP(du_disp),
+		SH_PFC_PIN_GROUP(hscif0_data_a),
+		SH_PFC_PIN_GROUP(hscif0_clk_a),
+		SH_PFC_PIN_GROUP(hscif0_ctrl_a),
+		SH_PFC_PIN_GROUP(hscif0_data_b),
+		SH_PFC_PIN_GROUP(hscif0_clk_b),
+		SH_PFC_PIN_GROUP(hscif1_data_a),
+		SH_PFC_PIN_GROUP(hscif1_clk_a),
+		SH_PFC_PIN_GROUP(hscif1_data_b),
+		SH_PFC_PIN_GROUP(hscif1_clk_b),
+		SH_PFC_PIN_GROUP(hscif1_ctrl_b),
+		SH_PFC_PIN_GROUP(hscif2_data_a),
+		SH_PFC_PIN_GROUP(hscif2_clk_a),
+		SH_PFC_PIN_GROUP(hscif2_ctrl_a),
+		SH_PFC_PIN_GROUP(hscif2_data_b),
+		SH_PFC_PIN_GROUP(hscif3_data_a),
+		SH_PFC_PIN_GROUP(hscif3_data_b),
+		SH_PFC_PIN_GROUP(hscif3_clk_b),
+		SH_PFC_PIN_GROUP(hscif3_data_c),
+		SH_PFC_PIN_GROUP(hscif3_clk_c),
+		SH_PFC_PIN_GROUP(hscif3_ctrl_c),
+		SH_PFC_PIN_GROUP(hscif3_data_d),
+		SH_PFC_PIN_GROUP(hscif3_data_e),
+		SH_PFC_PIN_GROUP(hscif3_ctrl_e),
+		SH_PFC_PIN_GROUP(hscif4_data_a),
+		SH_PFC_PIN_GROUP(hscif4_clk_a),
+		SH_PFC_PIN_GROUP(hscif4_ctrl_a),
+		SH_PFC_PIN_GROUP(hscif4_data_b),
+		SH_PFC_PIN_GROUP(hscif4_clk_b),
+		SH_PFC_PIN_GROUP(hscif4_data_c),
+		SH_PFC_PIN_GROUP(hscif4_data_d),
+		SH_PFC_PIN_GROUP(hscif4_data_e),
 		SH_PFC_PIN_GROUP(i2c1_a),
 		SH_PFC_PIN_GROUP(i2c1_b),
 		SH_PFC_PIN_GROUP(i2c1_c),
@@ -2586,6 +2901,52 @@  enum {
 	"du_disp",
 };
 
+static const char * const hscif0_groups[] = {
+	"hscif0_data_a",
+	"hscif0_clk_a",
+	"hscif0_ctrl_a",
+	"hscif0_data_b",
+	"hscif0_clk_b",
+};
+
+static const char * const hscif1_groups[] = {
+	"hscif1_data_a",
+	"hscif1_clk_a",
+	"hscif1_data_b",
+	"hscif1_clk_b",
+	"hscif1_ctrl_b",
+};
+
+static const char * const hscif2_groups[] = {
+	"hscif2_data_a",
+	"hscif2_clk_a",
+	"hscif2_ctrl_a",
+	"hscif2_data_b",
+};
+
+static const char * const hscif3_groups[] = {
+	"hscif3_data_a",
+	"hscif3_data_b",
+	"hscif3_clk_b",
+	"hscif3_data_c",
+	"hscif3_clk_c",
+	"hscif3_ctrl_c",
+	"hscif3_data_d",
+	"hscif3_data_e",
+	"hscif3_ctrl_e",
+};
+
+static const char * const hscif4_groups[] = {
+	"hscif4_data_a",
+	"hscif4_clk_a",
+	"hscif4_ctrl_a",
+	"hscif4_data_b",
+	"hscif4_clk_b",
+	"hscif4_data_c",
+	"hscif4_data_d",
+	"hscif4_data_e",
+};
+
 static const char * const i2c1_groups[] = {
 	"i2c1_a",
 	"i2c1_b",
@@ -2781,6 +3142,11 @@  enum {
 	.common = {
 		SH_PFC_FUNCTION(avb),
 		SH_PFC_FUNCTION(du),
+		SH_PFC_FUNCTION(hscif0),
+		SH_PFC_FUNCTION(hscif1),
+		SH_PFC_FUNCTION(hscif2),
+		SH_PFC_FUNCTION(hscif3),
+		SH_PFC_FUNCTION(hscif4),
 		SH_PFC_FUNCTION(i2c1),
 		SH_PFC_FUNCTION(i2c2),
 		SH_PFC_FUNCTION(i2c4),