| Message ID | 1539093467-12123-3-git-send-email-tdas@codeaurora.org (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add support for display port clocks and clock ops | expand |
Quoting Taniya Das (2018-10-09 06:57:47) > diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c > index 0cc4909..6d3136a 100644 > --- a/drivers/clk/qcom/dispcc-sdm845.c > +++ b/drivers/clk/qcom/dispcc-sdm845.c > @@ -128,6 +144,100 @@ enum { > }, > }; > > +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { > + .cmd_rcgr = 0x219c, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_2, > + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_aux_clk_src", > + .parent_names = disp_cc_parent_names_2, > + .num_parents = 2, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = { > + F(108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), > + F(180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), > + F(360000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), > + F(540000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { > + .cmd_rcgr = 0x2154, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_1, > + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_crypto_clk_src", > + .parent_names = disp_cc_parent_names_1, > + .num_parents = 4, > + .flags = CLK_GET_RATE_NOCACHE, Why? > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { > + F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > + F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > + F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), Are these in kHz? They really look like it and that's bad. Why do we need them at all? Just to make sure the display driver picks these exact frequencies? It seems like we could just pass whatever number comes in up to the parent and see what it can do. > + { } > +}; > + > +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { > + .cmd_rcgr = 0x2138, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_1, > + .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_link_clk_src", > + .parent_names = disp_cc_parent_names_1, > + .num_parents = 4, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { > + .cmd_rcgr = 0x2184, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_1, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_pixel1_clk_src", > + .parent_names = disp_cc_parent_names_1, > + .num_parents = 4, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_dp_ops, > + }, > +}; > + > +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { > + .cmd_rcgr = 0x216c, > + .mnd_width = 16, > + .hid_width = 5, > + .parent_map = disp_cc_parent_map_1, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_pixel_clk_src", > + .parent_names = disp_cc_parent_names_1, > + .num_parents = 4, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_dp_ops, > + }, > +}; > + > static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = { > F(19200000, P_BI_TCXO, 1, 0, 0), > { } > @@ -391,6 +501,115 @@ enum { > }, > }; > > +static struct clk_branch disp_cc_mdss_dp_aux_clk = { > + .halt_reg = 0x2054, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2054, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_aux_clk", > + .parent_names = (const char *[]){ > + "disp_cc_mdss_dp_aux_clk_src", > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_dp_crypto_clk = { > + .halt_reg = 0x2048, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2048, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_crypto_clk", > + .parent_names = (const char *[]){ > + "disp_cc_mdss_dp_crypto_clk_src", > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch disp_cc_mdss_dp_link_clk = { > + .halt_reg = 0x2040, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2040, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_link_clk", > + .parent_names = (const char *[]){ > + "disp_cc_mdss_dp_link_clk_src", > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 (div 4) */ Not sure what this comment is for. But it's interesting nonetheless. > +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { > + .halt_reg = 0x2044, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x2044, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "disp_cc_mdss_dp_link_intf_clk", > + .parent_names = (const char *[]){ > + "disp_cc_mdss_dp_link_clk_src", > + }, > + .num_parents = 1, > + .flags = CLK_GET_RATE_NOCACHE, Why? > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > +
Hello Stephen, On 10/10/2018 2:04 AM, Stephen Boyd wrote: > Quoting Taniya Das (2018-10-09 06:57:47) >> diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c >> index 0cc4909..6d3136a 100644 >> --- a/drivers/clk/qcom/dispcc-sdm845.c >> +++ b/drivers/clk/qcom/dispcc-sdm845.c >> @@ -128,6 +144,100 @@ enum { >> }, >> }; >> >> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { >> + F(19200000, P_BI_TCXO, 1, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { >> + .cmd_rcgr = 0x219c, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = disp_cc_parent_map_2, >> + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "disp_cc_mdss_dp_aux_clk_src", >> + .parent_names = disp_cc_parent_names_2, >> + .num_parents = 2, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = { >> + F(108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), >> + F(180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), >> + F(360000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), >> + F(540000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), >> + { } >> +}; >> + >> +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { >> + .cmd_rcgr = 0x2154, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = disp_cc_parent_map_1, >> + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "disp_cc_mdss_dp_crypto_clk_src", >> + .parent_names = disp_cc_parent_names_1, >> + .num_parents = 4, >> + .flags = CLK_GET_RATE_NOCACHE, > > Why? > >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { >> + F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >> + F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >> + F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >> + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > > Are these in kHz? They really look like it and that's bad. Why do we > need them at all? Just to make sure the display driver picks these exact > frequencies? It seems like we could just pass whatever number comes in > up to the parent and see what it can do. > Let me check back the reason we had to make this change. >> + { } >> +}; >> + >> +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { >> + .cmd_rcgr = 0x2138, >> + .mnd_width = 0, >> + .hid_width = 5, >> + .parent_map = disp_cc_parent_map_1, >> + .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "disp_cc_mdss_dp_link_clk_src", >> + .parent_names = disp_cc_parent_names_1, >> + .num_parents = 4, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_rcg2_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { >> + .cmd_rcgr = 0x2184, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = disp_cc_parent_map_1, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "disp_cc_mdss_dp_pixel1_clk_src", >> + .parent_names = disp_cc_parent_names_1, >> + .num_parents = 4, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_dp_ops, >> + }, >> +}; >> + >> +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { >> + .cmd_rcgr = 0x216c, >> + .mnd_width = 16, >> + .hid_width = 5, >> + .parent_map = disp_cc_parent_map_1, >> + .clkr.hw.init = &(struct clk_init_data){ >> + .name = "disp_cc_mdss_dp_pixel_clk_src", >> + .parent_names = disp_cc_parent_names_1, >> + .num_parents = 4, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_dp_ops, >> + }, >> +}; >> + >> static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = { >> F(19200000, P_BI_TCXO, 1, 0, 0), >> { } >> @@ -391,6 +501,115 @@ enum { >> }, >> }; >> >> +static struct clk_branch disp_cc_mdss_dp_aux_clk = { >> + .halt_reg = 0x2054, >> + .halt_check = BRANCH_HALT, >> + .clkr = { >> + .enable_reg = 0x2054, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "disp_cc_mdss_dp_aux_clk", >> + .parent_names = (const char *[]){ >> + "disp_cc_mdss_dp_aux_clk_src", >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_branch disp_cc_mdss_dp_crypto_clk = { >> + .halt_reg = 0x2048, >> + .halt_check = BRANCH_HALT, >> + .clkr = { >> + .enable_reg = 0x2048, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "disp_cc_mdss_dp_crypto_clk", >> + .parent_names = (const char *[]){ >> + "disp_cc_mdss_dp_crypto_clk_src", >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> +static struct clk_branch disp_cc_mdss_dp_link_clk = { >> + .halt_reg = 0x2040, >> + .halt_check = BRANCH_HALT, >> + .clkr = { >> + .enable_reg = 0x2040, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "disp_cc_mdss_dp_link_clk", >> + .parent_names = (const char *[]){ >> + "disp_cc_mdss_dp_link_clk_src", >> + }, >> + .num_parents = 1, >> + .flags = CLK_SET_RATE_PARENT, >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> + >> +/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 (div 4) */ > > Not sure what this comment is for. But it's interesting nonetheless. > >> +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { >> + .halt_reg = 0x2044, >> + .halt_check = BRANCH_HALT, >> + .clkr = { >> + .enable_reg = 0x2044, >> + .enable_mask = BIT(0), >> + .hw.init = &(struct clk_init_data){ >> + .name = "disp_cc_mdss_dp_link_intf_clk", >> + .parent_names = (const char *[]){ >> + "disp_cc_mdss_dp_link_clk_src", >> + }, >> + .num_parents = 1, >> + .flags = CLK_GET_RATE_NOCACHE, > > Why? > It was a requirement, but let me get back on this too. >> + .ops = &clk_branch2_ops, >> + }, >> + }, >> +}; >> +
Hello Stephen, On 2018-10-19 16:04, Taniya Das wrote: > Hello Stephen, > > On 10/10/2018 2:04 AM, Stephen Boyd wrote: >> Quoting Taniya Das (2018-10-09 06:57:47) >>> diff --git a/drivers/clk/qcom/dispcc-sdm845.c >>> b/drivers/clk/qcom/dispcc-sdm845.c >>> index 0cc4909..6d3136a 100644 >>> --- a/drivers/clk/qcom/dispcc-sdm845.c >>> +++ b/drivers/clk/qcom/dispcc-sdm845.c >>> @@ -128,6 +144,100 @@ enum { >>> }, >>> }; >>> >>> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { >>> + F(19200000, P_BI_TCXO, 1, 0, 0), >>> + { } >>> +}; >>> + >>> +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { >>> + .cmd_rcgr = 0x219c, >>> + .mnd_width = 0, >>> + .hid_width = 5, >>> + .parent_map = disp_cc_parent_map_2, >>> + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, >>> + .clkr.hw.init = &(struct clk_init_data){ >>> + .name = "disp_cc_mdss_dp_aux_clk_src", >>> + .parent_names = disp_cc_parent_names_2, >>> + .num_parents = 2, >>> + .flags = CLK_SET_RATE_PARENT, >>> + .ops = &clk_rcg2_ops, >>> + }, >>> +}; >>> + >>> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = >>> { >>> + F(108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), >>> + F(180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), >>> + F(360000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), >>> + F(540000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), >>> + { } >>> +}; >>> + >>> +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { >>> + .cmd_rcgr = 0x2154, >>> + .mnd_width = 0, >>> + .hid_width = 5, >>> + .parent_map = disp_cc_parent_map_1, >>> + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, >>> + .clkr.hw.init = &(struct clk_init_data){ >>> + .name = "disp_cc_mdss_dp_crypto_clk_src", >>> + .parent_names = disp_cc_parent_names_1, >>> + .num_parents = 4, >>> + .flags = CLK_GET_RATE_NOCACHE, >> >> Why? >> >>> + .ops = &clk_rcg2_ops, >>> + }, >>> +}; >>> + >>> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { >>> + F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >>> + F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >>> + F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >>> + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >> >> Are these in kHz? They really look like it and that's bad. Why do we >> need them at all? Just to make sure the display driver picks these >> exact >> frequencies? It seems like we could just pass whatever number comes in >> up to the parent and see what it can do. >> > > Let me check back the reason we had to make this change. We will need this flag since we reset/power-down the PLL every time we disconnect/connect the DP cable or during suspend/resume. Only with this flag, the calls to the PLL driver are properly called. > >>> + { } >>> +}; >>> + >>> +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { >>> + .cmd_rcgr = 0x2138, >>> + .mnd_width = 0, >>> + .hid_width = 5, >>> + .parent_map = disp_cc_parent_map_1, >>> + .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, >>> + .clkr.hw.init = &(struct clk_init_data){ >>> + .name = "disp_cc_mdss_dp_link_clk_src", >>> + .parent_names = disp_cc_parent_names_1, >>> + .num_parents = 4, >>> + .flags = CLK_SET_RATE_PARENT, >>> + .ops = &clk_rcg2_ops, >>> + }, >>> +}; >>> + >>> +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { >>> + .cmd_rcgr = 0x2184, >>> + .mnd_width = 16, >>> + .hid_width = 5, >>> + .parent_map = disp_cc_parent_map_1, >>> + .clkr.hw.init = &(struct clk_init_data){ >>> + .name = "disp_cc_mdss_dp_pixel1_clk_src", >>> + .parent_names = disp_cc_parent_names_1, >>> + .num_parents = 4, >>> + .flags = CLK_SET_RATE_PARENT, >>> + .ops = &clk_dp_ops, >>> + }, >>> +}; >>> + >>> +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { >>> + .cmd_rcgr = 0x216c, >>> + .mnd_width = 16, >>> + .hid_width = 5, >>> + .parent_map = disp_cc_parent_map_1, >>> + .clkr.hw.init = &(struct clk_init_data){ >>> + .name = "disp_cc_mdss_dp_pixel_clk_src", >>> + .parent_names = disp_cc_parent_names_1, >>> + .num_parents = 4, >>> + .flags = CLK_SET_RATE_PARENT, >>> + .ops = &clk_dp_ops, >>> + }, >>> +}; >>> + >>> static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = { >>> F(19200000, P_BI_TCXO, 1, 0, 0), >>> { } >>> @@ -391,6 +501,115 @@ enum { >>> }, >>> }; >>> >>> +static struct clk_branch disp_cc_mdss_dp_aux_clk = { >>> + .halt_reg = 0x2054, >>> + .halt_check = BRANCH_HALT, >>> + .clkr = { >>> + .enable_reg = 0x2054, >>> + .enable_mask = BIT(0), >>> + .hw.init = &(struct clk_init_data){ >>> + .name = "disp_cc_mdss_dp_aux_clk", >>> + .parent_names = (const char *[]){ >>> + "disp_cc_mdss_dp_aux_clk_src", >>> + }, >>> + .num_parents = 1, >>> + .flags = CLK_SET_RATE_PARENT, >>> + .ops = &clk_branch2_ops, >>> + }, >>> + }, >>> +}; >>> + >>> +static struct clk_branch disp_cc_mdss_dp_crypto_clk = { >>> + .halt_reg = 0x2048, >>> + .halt_check = BRANCH_HALT, >>> + .clkr = { >>> + .enable_reg = 0x2048, >>> + .enable_mask = BIT(0), >>> + .hw.init = &(struct clk_init_data){ >>> + .name = "disp_cc_mdss_dp_crypto_clk", >>> + .parent_names = (const char *[]){ >>> + "disp_cc_mdss_dp_crypto_clk_src", >>> + }, >>> + .num_parents = 1, >>> + .flags = CLK_SET_RATE_PARENT, >>> + .ops = &clk_branch2_ops, >>> + }, >>> + }, >>> +}; >>> + >>> +static struct clk_branch disp_cc_mdss_dp_link_clk = { >>> + .halt_reg = 0x2040, >>> + .halt_check = BRANCH_HALT, >>> + .clkr = { >>> + .enable_reg = 0x2040, >>> + .enable_mask = BIT(0), >>> + .hw.init = &(struct clk_init_data){ >>> + .name = "disp_cc_mdss_dp_link_clk", >>> + .parent_names = (const char *[]){ >>> + "disp_cc_mdss_dp_link_clk_src", >>> + }, >>> + .num_parents = 1, >>> + .flags = CLK_SET_RATE_PARENT, >>> + .ops = &clk_branch2_ops, >>> + }, >>> + }, >>> +}; >>> + >>> +/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 >>> (div 4) */ >> >> Not sure what this comment is for. But it's interesting nonetheless. >> >>> +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { >>> + .halt_reg = 0x2044, >>> + .halt_check = BRANCH_HALT, >>> + .clkr = { >>> + .enable_reg = 0x2044, >>> + .enable_mask = BIT(0), >>> + .hw.init = &(struct clk_init_data){ >>> + .name = "disp_cc_mdss_dp_link_intf_clk", >>> + .parent_names = (const char *[]){ >>> + "disp_cc_mdss_dp_link_clk_src", >>> + }, >>> + .num_parents = 1, >>> + .flags = CLK_GET_RATE_NOCACHE, >> >> Why? >> > > It was a requirement, but let me get back on this too. > I had a discussion with the Display Port teams and below is the requirement, This flag is required since we reset/power-down the PLL every time they disconnect/connect the DP cable or during suspend/resume. Only with this flag, the calls to the PLL driver properly. >>> + .ops = &clk_branch2_ops, >>> + }, >>> + }, >>> +}; >>> +
Quoting Taniya Das (2018-10-28 03:34:55) > Hello Stephen, > > On 2018-10-19 16:04, Taniya Das wrote: > > Hello Stephen, > > > > On 10/10/2018 2:04 AM, Stephen Boyd wrote: > >> Quoting Taniya Das (2018-10-09 06:57:47) > >>> diff --git a/drivers/clk/qcom/dispcc-sdm845.c > >>> b/drivers/clk/qcom/dispcc-sdm845.c > >>> index 0cc4909..6d3136a 100644 > >>> --- a/drivers/clk/qcom/dispcc-sdm845.c > >>> +++ b/drivers/clk/qcom/dispcc-sdm845.c > >>> @@ -128,6 +144,100 @@ enum { > >>> }, > >>> }; > >>> > >>> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { > >>> + F(19200000, P_BI_TCXO, 1, 0, 0), > >>> + { } > >>> +}; > >>> + > >>> +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { > >>> + .cmd_rcgr = 0x219c, > >>> + .mnd_width = 0, > >>> + .hid_width = 5, > >>> + .parent_map = disp_cc_parent_map_2, > >>> + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, > >>> + .clkr.hw.init = &(struct clk_init_data){ > >>> + .name = "disp_cc_mdss_dp_aux_clk_src", > >>> + .parent_names = disp_cc_parent_names_2, > >>> + .num_parents = 2, > >>> + .flags = CLK_SET_RATE_PARENT, > >>> + .ops = &clk_rcg2_ops, > >>> + }, > >>> +}; > >>> + > >>> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = > >>> { > >>> + F(108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), > >>> + F(180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), > >>> + F(360000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), > >>> + F(540000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), > >>> + { } > >>> +}; > >>> + > >>> +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { > >>> + .cmd_rcgr = 0x2154, > >>> + .mnd_width = 0, > >>> + .hid_width = 5, > >>> + .parent_map = disp_cc_parent_map_1, > >>> + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, > >>> + .clkr.hw.init = &(struct clk_init_data){ > >>> + .name = "disp_cc_mdss_dp_crypto_clk_src", > >>> + .parent_names = disp_cc_parent_names_1, > >>> + .num_parents = 4, > >>> + .flags = CLK_GET_RATE_NOCACHE, > >> > >> Why? > >> > >>> + .ops = &clk_rcg2_ops, > >>> + }, > >>> +}; > >>> + > >>> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { > >>> + F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > >>> + F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > >>> + F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > >>> + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > >> > >> Are these in kHz? They really look like it and that's bad. Why do we > >> need them at all? Just to make sure the display driver picks these > >> exact > >> frequencies? It seems like we could just pass whatever number comes in > >> up to the parent and see what it can do. > >> > > > > Let me check back the reason we had to make this change. > > We will need this flag since we reset/power-down the PLL every time we > disconnect/connect the DP cable or during suspend/resume. Only with this > flag, the calls to the PLL driver are properly called. What does this mean? I wanted to know about the weird frequencies listed above, and why it can't be done without a frequency table and direct rates passed up to the parent. > > > > >>> + { } > >>> +}; > >>> + > >>> +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { > >>> + .cmd_rcgr = 0x2138, > >>> + .mnd_width = 0, > >>> + .hid_width = 5, > >>> + .parent_map = disp_cc_parent_map_1, > >>> + .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, > >>> + .clkr.hw.init = &(struct clk_init_data){ > >>> + .name = "disp_cc_mdss_dp_link_clk_src", > >>> + .parent_names = disp_cc_parent_names_1, > >>> + .num_parents = 4, > >>> + .flags = CLK_SET_RATE_PARENT, > >>> + .ops = &clk_rcg2_ops, > >>> + }, > >>> +}; > >>> + > >>> +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { > >>> + .cmd_rcgr = 0x2184, > >>> + .mnd_width = 16, > >>> + .hid_width = 5, > >>> + .parent_map = disp_cc_parent_map_1, > >>> + .clkr.hw.init = &(struct clk_init_data){ > >>> + .name = "disp_cc_mdss_dp_pixel1_clk_src", > >>> + .parent_names = disp_cc_parent_names_1, > >>> + .num_parents = 4, > >>> + .flags = CLK_SET_RATE_PARENT, > >>> + .ops = &clk_dp_ops, > >>> + }, > >>> +}; > >>> + > >>> +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { > >>> + .cmd_rcgr = 0x216c, > >>> + .mnd_width = 16, > >>> + .hid_width = 5, > >>> + .parent_map = disp_cc_parent_map_1, > >>> + .clkr.hw.init = &(struct clk_init_data){ > >>> + .name = "disp_cc_mdss_dp_pixel_clk_src", > >>> + .parent_names = disp_cc_parent_names_1, > >>> + .num_parents = 4, > >>> + .flags = CLK_SET_RATE_PARENT, > >>> + .ops = &clk_dp_ops, > >>> + }, > >>> +}; > >>> + > >>> static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = { > >>> F(19200000, P_BI_TCXO, 1, 0, 0), > >>> { } > >>> @@ -391,6 +501,115 @@ enum { > >>> }, > >>> }; > >>> > >>> +static struct clk_branch disp_cc_mdss_dp_aux_clk = { > >>> + .halt_reg = 0x2054, > >>> + .halt_check = BRANCH_HALT, > >>> + .clkr = { > >>> + .enable_reg = 0x2054, > >>> + .enable_mask = BIT(0), > >>> + .hw.init = &(struct clk_init_data){ > >>> + .name = "disp_cc_mdss_dp_aux_clk", > >>> + .parent_names = (const char *[]){ > >>> + "disp_cc_mdss_dp_aux_clk_src", > >>> + }, > >>> + .num_parents = 1, > >>> + .flags = CLK_SET_RATE_PARENT, > >>> + .ops = &clk_branch2_ops, > >>> + }, > >>> + }, > >>> +}; > >>> + > >>> +static struct clk_branch disp_cc_mdss_dp_crypto_clk = { > >>> + .halt_reg = 0x2048, > >>> + .halt_check = BRANCH_HALT, > >>> + .clkr = { > >>> + .enable_reg = 0x2048, > >>> + .enable_mask = BIT(0), > >>> + .hw.init = &(struct clk_init_data){ > >>> + .name = "disp_cc_mdss_dp_crypto_clk", > >>> + .parent_names = (const char *[]){ > >>> + "disp_cc_mdss_dp_crypto_clk_src", > >>> + }, > >>> + .num_parents = 1, > >>> + .flags = CLK_SET_RATE_PARENT, > >>> + .ops = &clk_branch2_ops, > >>> + }, > >>> + }, > >>> +}; > >>> + > >>> +static struct clk_branch disp_cc_mdss_dp_link_clk = { > >>> + .halt_reg = 0x2040, > >>> + .halt_check = BRANCH_HALT, > >>> + .clkr = { > >>> + .enable_reg = 0x2040, > >>> + .enable_mask = BIT(0), > >>> + .hw.init = &(struct clk_init_data){ > >>> + .name = "disp_cc_mdss_dp_link_clk", > >>> + .parent_names = (const char *[]){ > >>> + "disp_cc_mdss_dp_link_clk_src", > >>> + }, > >>> + .num_parents = 1, > >>> + .flags = CLK_SET_RATE_PARENT, > >>> + .ops = &clk_branch2_ops, > >>> + }, > >>> + }, > >>> +}; > >>> + > >>> +/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 > >>> (div 4) */ > >> > >> Not sure what this comment is for. But it's interesting nonetheless. > >> > >>> +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { > >>> + .halt_reg = 0x2044, > >>> + .halt_check = BRANCH_HALT, > >>> + .clkr = { > >>> + .enable_reg = 0x2044, > >>> + .enable_mask = BIT(0), > >>> + .hw.init = &(struct clk_init_data){ > >>> + .name = "disp_cc_mdss_dp_link_intf_clk", > >>> + .parent_names = (const char *[]){ > >>> + "disp_cc_mdss_dp_link_clk_src", > >>> + }, > >>> + .num_parents = 1, > >>> + .flags = CLK_GET_RATE_NOCACHE, > >> > >> Why? > >> > > > > It was a requirement, but let me get back on this too. > > > I had a discussion with the Display Port teams and below is the requirement, > > This flag is required since we reset/power-down the PLL every time they > disconnect/connect the DP cable or during suspend/resume. > Only with this flag, the calls to the PLL driver properly. Ok. So that explains the get rate nocache flag. Can you please add a comment that explains that these clk registers here are lost across suspend/resume of the display device? It really sounds like these display clks are inside of the display power domain and thus they lose their state across the display power domain power down. It would be better if we could properly implement suspend/restore for these clk registers across suspend/resume of the display device so that we don't need this nocache flag and the display code can work together with the clk code here to restore the frequency to the clk. Is it really the case that the rcg here is always selecting a particular PLL and doing a div-1? Because that is very simple then to just write that setting again on genpd restore.
On 10/30/2018 12:13 AM, Stephen Boyd wrote: > Quoting Taniya Das (2018-10-28 03:34:55) >> Hello Stephen, >> >> On 2018-10-19 16:04, Taniya Das wrote: >>> Hello Stephen, >>> >>> On 10/10/2018 2:04 AM, Stephen Boyd wrote: >>>> Quoting Taniya Das (2018-10-09 06:57:47) >>>>> diff --git a/drivers/clk/qcom/dispcc-sdm845.c >>>>> b/drivers/clk/qcom/dispcc-sdm845.c >>>>> index 0cc4909..6d3136a 100644 >>>>> --- a/drivers/clk/qcom/dispcc-sdm845.c >>>>> +++ b/drivers/clk/qcom/dispcc-sdm845.c >>>>> @@ -128,6 +144,100 @@ enum { >>>>> }, >>>>> }; >>>>> >>>>> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { >>>>> + F(19200000, P_BI_TCXO, 1, 0, 0), >>>>> + { } >>>>> +}; >>>>> + >>>>> +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { >>>>> + .cmd_rcgr = 0x219c, >>>>> + .mnd_width = 0, >>>>> + .hid_width = 5, >>>>> + .parent_map = disp_cc_parent_map_2, >>>>> + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, >>>>> + .clkr.hw.init = &(struct clk_init_data){ >>>>> + .name = "disp_cc_mdss_dp_aux_clk_src", >>>>> + .parent_names = disp_cc_parent_names_2, >>>>> + .num_parents = 2, >>>>> + .flags = CLK_SET_RATE_PARENT, >>>>> + .ops = &clk_rcg2_ops, >>>>> + }, >>>>> +}; >>>>> + >>>>> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = >>>>> { >>>>> + F(108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), >>>>> + F(180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), >>>>> + F(360000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), >>>>> + F(540000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), >>>>> + { } >>>>> +}; >>>>> + >>>>> +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { >>>>> + .cmd_rcgr = 0x2154, >>>>> + .mnd_width = 0, >>>>> + .hid_width = 5, >>>>> + .parent_map = disp_cc_parent_map_1, >>>>> + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, >>>>> + .clkr.hw.init = &(struct clk_init_data){ >>>>> + .name = "disp_cc_mdss_dp_crypto_clk_src", >>>>> + .parent_names = disp_cc_parent_names_1, >>>>> + .num_parents = 4, >>>>> + .flags = CLK_GET_RATE_NOCACHE, >>>> >>>> Why? >>>> >>>>> + .ops = &clk_rcg2_ops, >>>>> + }, >>>>> +}; >>>>> + >>>>> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { >>>>> + F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >>>>> + F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >>>>> + F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >>>>> + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >>>> >>>> Are these in kHz? They really look like it and that's bad. Why do we >>>> need them at all? Just to make sure the display driver picks these >>>> exact >>>> frequencies? It seems like we could just pass whatever number comes in >>>> up to the parent and see what it can do. >>>> >>> >>> Let me check back the reason we had to make this change. >> >> We will need this flag since we reset/power-down the PLL every time we >> disconnect/connect the DP cable or during suspend/resume. Only with this >> flag, the calls to the PLL driver are properly called. > > What does this mean? I wanted to know about the weird frequencies listed > above, and why it can't be done without a frequency table and direct > rates passed up to the parent. > OOps, my bad :(. We added these changes to handle higher clock rates. These rates when greater than 4.3Ghz cannot be represented in 32bit variables. For DP, we already have 5.4G and 8.1GHz freq for VCO clock. We will need these Khz freq list in clock driver. Let me check if they can do something like the byte/pixel clocks of display. >> >>> >>>>> + { } >>>>> +}; >>>>> + >>>>> +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { >>>>> + .cmd_rcgr = 0x2138, >>>>> + .mnd_width = 0, >>>>> + .hid_width = 5, >>>>> + .parent_map = disp_cc_parent_map_1, >>>>> + .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, >>>>> + .clkr.hw.init = &(struct clk_init_data){ >>>>> + .name = "disp_cc_mdss_dp_link_clk_src", >>>>> + .parent_names = disp_cc_parent_names_1, >>>>> + .num_parents = 4, >>>>> + .flags = CLK_SET_RATE_PARENT, >>>>> + .ops = &clk_rcg2_ops, >>>>> + }, >>>>> +}; >>>>> + >>>>> +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { >>>>> + .cmd_rcgr = 0x2184, >>>>> + .mnd_width = 16, >>>>> + .hid_width = 5, >>>>> + .parent_map = disp_cc_parent_map_1, >>>>> + .clkr.hw.init = &(struct clk_init_data){ >>>>> + .name = "disp_cc_mdss_dp_pixel1_clk_src", >>>>> + .parent_names = disp_cc_parent_names_1, >>>>> + .num_parents = 4, >>>>> + .flags = CLK_SET_RATE_PARENT, >>>>> + .ops = &clk_dp_ops, >>>>> + }, >>>>> +}; >>>>> + >>>>> +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { >>>>> + .cmd_rcgr = 0x216c, >>>>> + .mnd_width = 16, >>>>> + .hid_width = 5, >>>>> + .parent_map = disp_cc_parent_map_1, >>>>> + .clkr.hw.init = &(struct clk_init_data){ >>>>> + .name = "disp_cc_mdss_dp_pixel_clk_src", >>>>> + .parent_names = disp_cc_parent_names_1, >>>>> + .num_parents = 4, >>>>> + .flags = CLK_SET_RATE_PARENT, >>>>> + .ops = &clk_dp_ops, >>>>> + }, >>>>> +}; >>>>> + >>>>> static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = { >>>>> F(19200000, P_BI_TCXO, 1, 0, 0), >>>>> { } >>>>> @@ -391,6 +501,115 @@ enum { >>>>> }, >>>>> }; >>>>> >>>>> +static struct clk_branch disp_cc_mdss_dp_aux_clk = { >>>>> + .halt_reg = 0x2054, >>>>> + .halt_check = BRANCH_HALT, >>>>> + .clkr = { >>>>> + .enable_reg = 0x2054, >>>>> + .enable_mask = BIT(0), >>>>> + .hw.init = &(struct clk_init_data){ >>>>> + .name = "disp_cc_mdss_dp_aux_clk", >>>>> + .parent_names = (const char *[]){ >>>>> + "disp_cc_mdss_dp_aux_clk_src", >>>>> + }, >>>>> + .num_parents = 1, >>>>> + .flags = CLK_SET_RATE_PARENT, >>>>> + .ops = &clk_branch2_ops, >>>>> + }, >>>>> + }, >>>>> +}; >>>>> + >>>>> +static struct clk_branch disp_cc_mdss_dp_crypto_clk = { >>>>> + .halt_reg = 0x2048, >>>>> + .halt_check = BRANCH_HALT, >>>>> + .clkr = { >>>>> + .enable_reg = 0x2048, >>>>> + .enable_mask = BIT(0), >>>>> + .hw.init = &(struct clk_init_data){ >>>>> + .name = "disp_cc_mdss_dp_crypto_clk", >>>>> + .parent_names = (const char *[]){ >>>>> + "disp_cc_mdss_dp_crypto_clk_src", >>>>> + }, >>>>> + .num_parents = 1, >>>>> + .flags = CLK_SET_RATE_PARENT, >>>>> + .ops = &clk_branch2_ops, >>>>> + }, >>>>> + }, >>>>> +}; >>>>> + >>>>> +static struct clk_branch disp_cc_mdss_dp_link_clk = { >>>>> + .halt_reg = 0x2040, >>>>> + .halt_check = BRANCH_HALT, >>>>> + .clkr = { >>>>> + .enable_reg = 0x2040, >>>>> + .enable_mask = BIT(0), >>>>> + .hw.init = &(struct clk_init_data){ >>>>> + .name = "disp_cc_mdss_dp_link_clk", >>>>> + .parent_names = (const char *[]){ >>>>> + "disp_cc_mdss_dp_link_clk_src", >>>>> + }, >>>>> + .num_parents = 1, >>>>> + .flags = CLK_SET_RATE_PARENT, >>>>> + .ops = &clk_branch2_ops, >>>>> + }, >>>>> + }, >>>>> +}; >>>>> + >>>>> +/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 >>>>> (div 4) */ >>>> >>>> Not sure what this comment is for. But it's interesting nonetheless. >>>> >>>>> +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { >>>>> + .halt_reg = 0x2044, >>>>> + .halt_check = BRANCH_HALT, >>>>> + .clkr = { >>>>> + .enable_reg = 0x2044, >>>>> + .enable_mask = BIT(0), >>>>> + .hw.init = &(struct clk_init_data){ >>>>> + .name = "disp_cc_mdss_dp_link_intf_clk", >>>>> + .parent_names = (const char *[]){ >>>>> + "disp_cc_mdss_dp_link_clk_src", >>>>> + }, >>>>> + .num_parents = 1, >>>>> + .flags = CLK_GET_RATE_NOCACHE, >>>> >>>> Why? >>>> >>> >>> It was a requirement, but let me get back on this too. >>> >> I had a discussion with the Display Port teams and below is the requirement, >> >> This flag is required since we reset/power-down the PLL every time they >> disconnect/connect the DP cable or during suspend/resume. >> Only with this flag, the calls to the PLL driver properly. > > Ok. So that explains the get rate nocache flag. Can you please add a > comment that explains that these clk registers here are lost across > suspend/resume of the display device? It really sounds like these > display clks are inside of the display power domain and thus they lose > their state across the display power domain power down. It would be > better if we could properly implement suspend/restore for these clk > registers across suspend/resume of the display device so that we don't > need this nocache flag and the display code can work together with the > clk code here to restore the frequency to the clk. > > Is it really the case that the rcg here is always selecting a particular > PLL and doing a div-1? Because that is very simple then to just write > that setting again on genpd restore. >
Quoting Taniya Das (2018-10-29 23:01:44) > On 10/30/2018 12:13 AM, Stephen Boyd wrote: > > Quoting Taniya Das (2018-10-28 03:34:55) > >> On 2018-10-19 16:04, Taniya Das wrote: > >>> On 10/10/2018 2:04 AM, Stephen Boyd wrote: > >>>> Quoting Taniya Das (2018-10-09 06:57:47) > >>>>> diff --git a/drivers/clk/qcom/dispcc-sdm845.c > >>>>> b/drivers/clk/qcom/dispcc-sdm845.c > >>>>> index 0cc4909..6d3136a 100644 > >>>>> --- a/drivers/clk/qcom/dispcc-sdm845.c > >>>>> +++ b/drivers/clk/qcom/dispcc-sdm845.c > >>>>> + }, > >>>>> +}; > >>>>> + > >>>>> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { > >>>>> + F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > >>>>> + F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > >>>>> + F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > >>>>> + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), > >>>> > >>>> Are these in kHz? They really look like it and that's bad. Why do we > >>>> need them at all? Just to make sure the display driver picks these > >>>> exact > >>>> frequencies? It seems like we could just pass whatever number comes in > >>>> up to the parent and see what it can do. > >>>> > >>> > >>> Let me check back the reason we had to make this change. > >> > >> We will need this flag since we reset/power-down the PLL every time we > >> disconnect/connect the DP cable or during suspend/resume. Only with this > >> flag, the calls to the PLL driver are properly called. > > > > What does this mean? I wanted to know about the weird frequencies listed > > above, and why it can't be done without a frequency table and direct > > rates passed up to the parent. > > > > OOps, my bad :(. > > We added these changes to handle higher clock rates. These rates when > greater than 4.3Ghz cannot be represented in 32bit variables. For DP, we > already have 5.4G and 8.1GHz freq for VCO clock. We will need these Khz > freq list in clock driver. > Let me check if they can do something like the byte/pixel clocks of > display. Well then we really should just throw away the freq table here and have rcg ops that pass the frequency up to the display PLL. Also, those numbers look like gigabits per second (Gbit/s) for the DP spec which isn't exactly the same as a clk frequency. What frequency does the PLL run at for these various DP link speeds?
+ Chandan from Display Port team, On 10/30/2018 10:03 PM, Stephen Boyd wrote: > Quoting Taniya Das (2018-10-29 23:01:44) >> On 10/30/2018 12:13 AM, Stephen Boyd wrote: >>> Quoting Taniya Das (2018-10-28 03:34:55) >>>> On 2018-10-19 16:04, Taniya Das wrote: >>>>> On 10/10/2018 2:04 AM, Stephen Boyd wrote: >>>>>> Quoting Taniya Das (2018-10-09 06:57:47) >>>>>>> diff --git a/drivers/clk/qcom/dispcc-sdm845.c >>>>>>> b/drivers/clk/qcom/dispcc-sdm845.c >>>>>>> index 0cc4909..6d3136a 100644 >>>>>>> --- a/drivers/clk/qcom/dispcc-sdm845.c >>>>>>> +++ b/drivers/clk/qcom/dispcc-sdm845.c >>>>>>> + }, >>>>>>> +}; >>>>>>> + >>>>>>> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { >>>>>>> + F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >>>>>>> + F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >>>>>>> + F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >>>>>>> + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >>>>>> >>>>>> Are these in kHz? They really look like it and that's bad. Why do we >>>>>> need them at all? Just to make sure the display driver picks these >>>>>> exact >>>>>> frequencies? It seems like we could just pass whatever number comes in >>>>>> up to the parent and see what it can do. >>>>>> >>>>> >>>>> Let me check back the reason we had to make this change. >>>> >>>> We will need this flag since we reset/power-down the PLL every time we >>>> disconnect/connect the DP cable or during suspend/resume. Only with this >>>> flag, the calls to the PLL driver are properly called. >>> >>> What does this mean? I wanted to know about the weird frequencies listed >>> above, and why it can't be done without a frequency table and direct >>> rates passed up to the parent. >>> >> >> OOps, my bad :(. >> >> We added these changes to handle higher clock rates. These rates when >> greater than 4.3Ghz cannot be represented in 32bit variables. For DP, we >> already have 5.4G and 8.1GHz freq for VCO clock. We will need these Khz >> freq list in clock driver. >> Let me check if they can do something like the byte/pixel clocks of >> display. > > Well then we really should just throw away the freq table here and have > rcg ops that pass the frequency up to the display PLL. Also, those > numbers look like gigabits per second (Gbit/s) for the DP spec which > isn't exactly the same as a clk frequency. What frequency does the PLL > run at for these various DP link speeds? > Could you please help with the above query from Stephen?
Quoting Taniya Das (2018-10-31 22:02:22) > + Chandan from Display Port team, > > On 10/30/2018 10:03 PM, Stephen Boyd wrote: > > Also, those > > numbers look like gigabits per second (Gbit/s) for the DP spec which > > isn't exactly the same as a clk frequency. What frequency does the PLL > > run at for these various DP link speeds? > > > Could you please help with the above query from Stephen? Can I safely assume that it matches the link rate shown on Wikipedia for display port[1]? I.e. RBR (Reduced Bit Rate): 1.62 Gbit/s bandwidth per lane (162 MHz link symbol rate) HBR (High Bit Rate): 2.70 Gbit/s bandwidth per lane (270 MHz link symbol rate) HBR2 (High Bit Rate 2): 5.40 Gbit/s bandwidth per lane (540 MHz link symbol rate), introduced in DP 1.2 HBR3 (High Bit Rate 3): 8.10 Gbit/s bandwidth per lane (810 MHz link symbol rate), introduced in DP 1.3 So then they're MHz but the table is written in kHz when it should be written in Hz. Either way, the table can be removed and then we just need to fix the DP PHY PLL code to accept Hz instead of kHz. [1] https://en.wikipedia.org/wiki/DisplayPort#Main_link
On 2018-11-06 09:08, Stephen Boyd wrote: > Quoting Taniya Das (2018-10-31 22:02:22) >> + Chandan from Display Port team, >> >> On 10/30/2018 10:03 PM, Stephen Boyd wrote: >> > Also, those >> > numbers look like gigabits per second (Gbit/s) for the DP spec which >> > isn't exactly the same as a clk frequency. What frequency does the PLL >> > run at for these various DP link speeds? >> > >> Could you please help with the above query from Stephen? Hello Stephen, For DP link speed of 5.4Gbit/s, the PLL will be running at 10.8 Ghz. For all the other DP link speeds, the PLL will be running at 8.1 Ghz. > > Can I safely assume that it matches the link rate shown on Wikipedia > for > display port[1]? I.e. > > RBR (Reduced Bit Rate): 1.62 Gbit/s bandwidth per lane (162 MHz link > symbol rate) > HBR (High Bit Rate): 2.70 Gbit/s bandwidth per lane (270 MHz link > symbol rate) > HBR2 (High Bit Rate 2): 5.40 Gbit/s bandwidth per lane (540 MHz link > symbol rate), introduced in DP 1.2 > HBR3 (High Bit Rate 3): 8.10 Gbit/s bandwidth per lane (810 MHz link > symbol rate), introduced in DP 1.3 > > So then they're MHz but the table is written in kHz when it should be > written in Hz. Either way, the table can be removed and then we just > need to fix the DP PHY PLL code to accept Hz instead of kHz. > > [1] https://en.wikipedia.org/wiki/DisplayPort#Main_link
Hello Stephen, On 2018-10-29 11:43, Stephen Boyd wrote: > Quoting Taniya Das (2018-10-28 03:34:55) >> Hello Stephen, >> >> On 2018-10-19 16:04, Taniya Das wrote: >> > Hello Stephen, >> > /snip >> >>> +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { >> >>> + .cmd_rcgr = 0x2154, >> >>> + .mnd_width = 0, >> >>> + .hid_width = 5, >> >>> + .parent_map = disp_cc_parent_map_1, >> >>> + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, >> >>> + .clkr.hw.init = &(struct clk_init_data){ >> >>> + .name = "disp_cc_mdss_dp_crypto_clk_src", >> >>> + .parent_names = disp_cc_parent_names_1, >> >>> + .num_parents = 4, >> >>> + .flags = CLK_GET_RATE_NOCACHE, >> >> >> >> Why? >> >> >> >>> + .ops = &clk_rcg2_ops, >> >>> + }, >> >>> +}; >> >>> + >> >>> +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { >> >>> + F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >> >>> + F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >> >>> + F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >> >>> + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), >> >> >> >> Are these in kHz? They really look like it and that's bad. Why do we >> >> need them at all? Just to make sure the display driver picks these >> >> exact >> >> frequencies? It seems like we could just pass whatever number comes in >> >> up to the parent and see what it can do. >> >> >> > >> > Let me check back the reason we had to make this change. >> >> We will need this flag since we reset/power-down the PLL every time we >> disconnect/connect the DP cable or during suspend/resume. Only with >> this >> flag, the calls to the PLL driver are properly called. > > What does this mean? I wanted to know about the weird frequencies > listed > above, and why it can't be done without a frequency table and direct > rates passed up to the parent. > /snip >> >> >> >>> +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { >> >>> + .halt_reg = 0x2044, >> >>> + .halt_check = BRANCH_HALT, >> >>> + .clkr = { >> >>> + .enable_reg = 0x2044, >> >>> + .enable_mask = BIT(0), >> >>> + .hw.init = &(struct clk_init_data){ >> >>> + .name = "disp_cc_mdss_dp_link_intf_clk", >> >>> + .parent_names = (const char *[]){ >> >>> + "disp_cc_mdss_dp_link_clk_src", >> >>> + }, >> >>> + .num_parents = 1, >> >>> + .flags = CLK_GET_RATE_NOCACHE, >> >> >> >> Why? >> >> >> > >> > It was a requirement, but let me get back on this too. >> > >> I had a discussion with the Display Port teams and below is the >> requirement, >> >> This flag is required since we reset/power-down the PLL every time >> they >> disconnect/connect the DP cable or during suspend/resume. >> Only with this flag, the calls to the PLL driver properly. > > Ok. So that explains the get rate nocache flag. Can you please add a > comment that explains that these clk registers here are lost across > suspend/resume of the display device? It really sounds like these > display clks are inside of the display power domain and thus they lose > their state across the display power domain power down. It would be > better if we could properly implement suspend/restore for these clk > registers across suspend/resume of the display device so that we don't > need this nocache flag and the display code can work together with the > clk code here to restore the frequency to the clk. We already handle the suspend/restore for these clk registers in Dp PLL domain. Without the "NOCACHE_FLAG", and if we are requesting the same clock rate for any of the clocks, the set_rate call never reaches the DP PLL Ops. I am not clear on what you are suggesting for removing the "NOCACHE_FLAG" for the DisplayPort clocks. Are you suggesting design changes in DP PLL driver or in dispcc-driver? Can you please provide more details? thanks Chandan > > Is it really the case that the rcg here is always selecting a > particular > PLL and doing a div-1? Because that is very simple then to just write > that setting again on genpd restore.
Quoting chandanu@codeaurora.org (2019-02-01 16:05:55) > On 2018-10-29 11:43, Stephen Boyd wrote: > > Quoting Taniya Das (2018-10-28 03:34:55) > >> On 2018-10-19 16:04, Taniya Das wrote: > > >> >> > >> >>> +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { > >> >>> + .halt_reg = 0x2044, > >> >>> + .halt_check = BRANCH_HALT, > >> >>> + .clkr = { > >> >>> + .enable_reg = 0x2044, > >> >>> + .enable_mask = BIT(0), > >> >>> + .hw.init = &(struct clk_init_data){ > >> >>> + .name = "disp_cc_mdss_dp_link_intf_clk", > >> >>> + .parent_names = (const char *[]){ > >> >>> + "disp_cc_mdss_dp_link_clk_src", > >> >>> + }, > >> >>> + .num_parents = 1, > >> >>> + .flags = CLK_GET_RATE_NOCACHE, > >> >> > >> >> Why? > >> >> > >> > > >> > It was a requirement, but let me get back on this too. > >> > > >> I had a discussion with the Display Port teams and below is the > >> requirement, > >> > >> This flag is required since we reset/power-down the PLL every time > >> they > >> disconnect/connect the DP cable or during suspend/resume. > >> Only with this flag, the calls to the PLL driver properly. > > > > Ok. So that explains the get rate nocache flag. Can you please add a > > comment that explains that these clk registers here are lost across > > suspend/resume of the display device? It really sounds like these > > display clks are inside of the display power domain and thus they lose > > their state across the display power domain power down. It would be > > better if we could properly implement suspend/restore for these clk > > registers across suspend/resume of the display device so that we don't > > need this nocache flag and the display code can work together with the > > clk code here to restore the frequency to the clk. > This patch came again and it didn't have any comments to this effect in the code around the flag. > > We already handle the suspend/restore for these clk registers > in Dp PLL domain. Without the "NOCACHE_FLAG", and if we are requesting > the same clock rate > for any of the clocks, the set_rate call never reaches the DP PLL Ops. So do you restore the frequency of the PLL manually? Or that is done by calling clk_set_rate() on the leaf clk again? > > I am not clear on what you are suggesting for removing the > "NOCACHE_FLAG" for > the DisplayPort clocks. Are you suggesting design changes in DP PLL > driver or in dispcc-driver? > Can you please provide more details? > I'm suggesting that the clk framework needs to be told that the PLL has lost the rate and thus should do a save/restore of the registers so that the clk framework can be back in sync with the clk hardware. Maybe it's as simple as calling clk_set_rate(&pll, XO_RATE) or clk_set_parent(&pll, &xo_clk), so that we can recalc the rate down the tree and fix up the child clk frequencies. Or, maybe we need to add some sort of mechanism to the clk framework so it can be told that the frequency here has changed. Or we need to add a hook in the power domain for the DP PLL to tell the clk framework that the clk has changed rate and thus should recalc down to the children. Something like this, instead of an obtuse flag that tells us very little about what's going on.
diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c index 0cc4909..6d3136a 100644 --- a/drivers/clk/qcom/dispcc-sdm845.c +++ b/drivers/clk/qcom/dispcc-sdm845.c @@ -29,6 +29,8 @@ enum { P_DSI1_PHY_PLL_OUT_DSICLK, P_GPLL0_OUT_MAIN, P_GPLL0_OUT_MAIN_DIV, + P_DP_PHY_PLL_LINK_CLK, + P_DP_PHY_PLL_VCO_DIV_CLK, }; static const struct parent_map disp_cc_parent_map_0[] = { @@ -45,6 +47,20 @@ enum { "core_bi_pll_test_se", }; +static const struct parent_map disp_cc_parent_map_1[] = { + { P_BI_TCXO, 0 }, + { P_DP_PHY_PLL_LINK_CLK, 1 }, + { P_DP_PHY_PLL_VCO_DIV_CLK, 2 }, + { P_CORE_BI_PLL_TEST_SE, 7 }, +}; + +static const char * const disp_cc_parent_names_1[] = { + "bi_tcxo", + "dp_link_clk_divsel_ten", + "dp_vco_divided_clk_src_mux", + "core_bi_pll_test_se", +}; + static const struct parent_map disp_cc_parent_map_2[] = { { P_BI_TCXO, 0 }, { P_CORE_BI_PLL_TEST_SE, 7 }, @@ -128,6 +144,100 @@ enum { }, }; +static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = { + .cmd_rcgr = 0x219c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_2, + .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux_clk_src", + .parent_names = disp_cc_parent_names_2, + .num_parents = 2, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_crypto_clk_src[] = { + F(108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), + F(180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), + F(360000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), + F(540000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { + .cmd_rcgr = 0x2154, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_crypto_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_crypto_clk_src", + .parent_names = disp_cc_parent_names_1, + .num_parents = 4, + .flags = CLK_GET_RATE_NOCACHE, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_disp_cc_mdss_dp_link_clk_src[] = { + F(162000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), + F(270000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), + F(540000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), + F(810000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { + .cmd_rcgr = 0x2138, + .mnd_width = 0, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .freq_tbl = ftbl_disp_cc_mdss_dp_link_clk_src, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_clk_src", + .parent_names = disp_cc_parent_names_1, + .num_parents = 4, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = { + .cmd_rcgr = 0x2184, + .mnd_width = 16, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel1_clk_src", + .parent_names = disp_cc_parent_names_1, + .num_parents = 4, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_dp_ops, + }, +}; + +static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = { + .cmd_rcgr = 0x216c, + .mnd_width = 16, + .hid_width = 5, + .parent_map = disp_cc_parent_map_1, + .clkr.hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel_clk_src", + .parent_names = disp_cc_parent_names_1, + .num_parents = 4, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_dp_ops, + }, +}; + static const struct freq_tbl ftbl_disp_cc_mdss_esc0_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), { } @@ -391,6 +501,115 @@ enum { }, }; +static struct clk_branch disp_cc_mdss_dp_aux_clk = { + .halt_reg = 0x2054, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2054, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_aux_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_dp_aux_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_crypto_clk = { + .halt_reg = 0x2048, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2048, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_crypto_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_dp_crypto_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_link_clk = { + .halt_reg = 0x2040, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2040, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_dp_link_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +/* reset state of disp_cc_mdss_dp_link_div_clk_src divider is 0x3 (div 4) */ +static struct clk_branch disp_cc_mdss_dp_link_intf_clk = { + .halt_reg = 0x2044, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2044, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_link_intf_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_dp_link_clk_src", + }, + .num_parents = 1, + .flags = CLK_GET_RATE_NOCACHE, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel1_clk = { + .halt_reg = 0x2050, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x2050, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel1_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_dp_pixel1_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch disp_cc_mdss_dp_pixel_clk = { + .halt_reg = 0x204c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x204c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data){ + .name = "disp_cc_mdss_dp_pixel_clk", + .parent_names = (const char *[]){ + "disp_cc_mdss_dp_pixel_clk_src", + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch disp_cc_mdss_esc0_clk = { .halt_reg = 0x2038, .halt_check = BRANCH_HALT, @@ -589,6 +808,19 @@ enum { [DISP_CC_MDSS_BYTE1_INTF_CLK] = &disp_cc_mdss_byte1_intf_clk.clkr, [DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &disp_cc_mdss_byte1_div_clk_src.clkr, + [DISP_CC_MDSS_DP_AUX_CLK] = &disp_cc_mdss_dp_aux_clk.clkr, + [DISP_CC_MDSS_DP_AUX_CLK_SRC] = &disp_cc_mdss_dp_aux_clk_src.clkr, + [DISP_CC_MDSS_DP_CRYPTO_CLK] = &disp_cc_mdss_dp_crypto_clk.clkr, + [DISP_CC_MDSS_DP_CRYPTO_CLK_SRC] = + &disp_cc_mdss_dp_crypto_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_CLK] = &disp_cc_mdss_dp_link_clk.clkr, + [DISP_CC_MDSS_DP_LINK_CLK_SRC] = &disp_cc_mdss_dp_link_clk_src.clkr, + [DISP_CC_MDSS_DP_LINK_INTF_CLK] = &disp_cc_mdss_dp_link_intf_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL1_CLK] = &disp_cc_mdss_dp_pixel1_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL1_CLK_SRC] = + &disp_cc_mdss_dp_pixel1_clk_src.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr, + [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr, [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr, [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr, [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr, diff --git a/include/dt-bindings/clock/qcom,dispcc-sdm845.h b/include/dt-bindings/clock/qcom,dispcc-sdm845.h index 11eed4b..526d98a 100644 --- a/include/dt-bindings/clock/qcom,dispcc-sdm845.h +++ b/include/dt-bindings/clock/qcom,dispcc-sdm845.h @@ -35,6 +35,17 @@ #define DISP_CC_PLL0 25 #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26 #define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27 +#define DISP_CC_MDSS_DP_AUX_CLK 28 +#define DISP_CC_MDSS_DP_AUX_CLK_SRC 29 +#define DISP_CC_MDSS_DP_CRYPTO_CLK 30 +#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 31 +#define DISP_CC_MDSS_DP_LINK_CLK 32 +#define DISP_CC_MDSS_DP_LINK_CLK_SRC 33 +#define DISP_CC_MDSS_DP_LINK_INTF_CLK 34 +#define DISP_CC_MDSS_DP_PIXEL1_CLK 35 +#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 36 +#define DISP_CC_MDSS_DP_PIXEL_CLK 37 +#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 38 /* DISP_CC Reset */ #define DISP_CC_MDSS_RSCC_BCR 0
SDM845 dispcc supports RCG and CBCRs for display port, so add support for the same. Signed-off-by: Taniya Das <tdas@codeaurora.org> --- drivers/clk/qcom/dispcc-sdm845.c | 232 +++++++++++++++++++++++++ include/dt-bindings/clock/qcom,dispcc-sdm845.h | 11 ++ 2 files changed, 243 insertions(+) -- Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.