| Message ID | 20181026173544.136037-5-evgreen@chromium.org (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | arm64: dts: qcom: sdm845: Add UFS DT nodes | expand |
Quoting Evan Green (2018-10-26 10:35:43) > diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts > index eedfaf8922e2..d5fddea71a85 100644 > --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts > +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts > @@ -356,6 +356,20 @@ > status = "okay"; > }; > > +&ufshc1 { > + status = "okay"; > + > + vcc-supply = <&vreg_l20a_2p95>; > + vcc-max-microamp = <600000>; Is this board dependent? I would guess this is SoC specific and not board specific. > +}; > + > +&ufsphy1 { > + status = "okay"; > + > + vdda-phy-supply = <&vdda_ufs1_core>; > + vdda-pll-supply = <&vdda_ufs1_1p2>; These two properties can be specified in the SoC dtsi file instead of each board variant file. This way we don't have to specify the things that are SoC independent in each board file. The board integrator just has to attach the labels to the right regulator nodes, in this case vdda_ufs1_core and vdda_ufs1_1p2, and then the sdm845.dtsi file will be matched up with the right regulator automatically. It's also nice so that board integrators don't have to know anything besides what regulator goes to what pin on the SoC. The status property has to stay of course.
Hi, On Mon, Nov 19, 2018 at 11:19 AM Stephen Boyd <swboyd@chromium.org> wrote: > > Quoting Evan Green (2018-10-26 10:35:43) > > diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts > > index eedfaf8922e2..d5fddea71a85 100644 > > --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts > > +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts > > @@ -356,6 +356,20 @@ > > status = "okay"; > > }; > > > > +&ufshc1 { > > + status = "okay"; > > + > > + vcc-supply = <&vreg_l20a_2p95>; > > + vcc-max-microamp = <600000>; > > Is this board dependent? I would guess this is SoC specific and not > board specific. > > > +}; > > + > > +&ufsphy1 { > > + status = "okay"; > > + > > + vdda-phy-supply = <&vdda_ufs1_core>; > > + vdda-pll-supply = <&vdda_ufs1_1p2>; > > These two properties can be specified in the SoC dtsi file instead of > each board variant file. This way we don't have to specify the things > that are SoC independent in each board file. The board integrator just > has to attach the labels to the right regulator nodes, in this case > vdda_ufs1_core and vdda_ufs1_1p2, and then the sdm845.dtsi file will be > matched up with the right regulator automatically. It's also nice so > that board integrators don't have to know anything besides what > regulator goes to what pin on the SoC. This is an interesting proposal and it feels like we have to consider the tradeoffs. I agree that it would be nice not to have to specify this in every single board .dts file, but at the same time what if you've got a board that doesn't use UFS? Such a board would bother adding the labels "vdda_ufs1_core" and "vdda_ufs1_1p2". This would lead to a compile error in the device tree bindings. That seems pretty undesirable. +Bjorn since I think Bjorn wasn't a huge fan of the labels like "vdda_ufs1_core" to start with. -Doug
Quoting Doug Anderson (2018-11-19 11:25:08) > On Mon, Nov 19, 2018 at 11:19 AM Stephen Boyd <swboyd@chromium.org> wrote: > > > > Quoting Evan Green (2018-10-26 10:35:43) > > > > > +}; > > > + > > > +&ufsphy1 { > > > + status = "okay"; > > > + > > > + vdda-phy-supply = <&vdda_ufs1_core>; > > > + vdda-pll-supply = <&vdda_ufs1_1p2>; > > > > These two properties can be specified in the SoC dtsi file instead of > > each board variant file. This way we don't have to specify the things > > that are SoC independent in each board file. The board integrator just > > has to attach the labels to the right regulator nodes, in this case > > vdda_ufs1_core and vdda_ufs1_1p2, and then the sdm845.dtsi file will be > > matched up with the right regulator automatically. It's also nice so > > that board integrators don't have to know anything besides what > > regulator goes to what pin on the SoC. > > This is an interesting proposal and it feels like we have to consider > the tradeoffs. > > I agree that it would be nice not to have to specify this in every > single board .dts file, but at the same time what if you've got a > board that doesn't use UFS? Such a board would bother adding the > labels "vdda_ufs1_core" and "vdda_ufs1_1p2". This would lead to a > compile error in the device tree bindings. That seems pretty > undesirable. > A workaround for this somewhat rare case would be to specify /delete-property/ on those nodes that aren't used. Unless that can't even work because the phandle is parsed before properties are deleted? I haven't tried. Or we could try to have dtc ignore broken phandles in status = "disabled" nodes or omit them entirely from the dtb so this isn't a problem. Either way, I would push for making it easier for the users of the SoC to not need to know the SoC internal details too much and rely on the SoC dtsi file to get it right. From the user perspective it's just a bunch of pins connected to something. We could also have a 0 volt "ground" regulator for any grounded/unconnected pins if that helps. It could be marked as status = "disabled" so that no runtime code is used while dtc is still happy to have the disabled node with a label.
On Mon 19 Nov 11:42 PST 2018, Stephen Boyd wrote: > Quoting Doug Anderson (2018-11-19 11:25:08) > > On Mon, Nov 19, 2018 at 11:19 AM Stephen Boyd <swboyd@chromium.org> wrote: > > > > > > Quoting Evan Green (2018-10-26 10:35:43) > > > > > > > +}; > > > > + > > > > +&ufsphy1 { > > > > + status = "okay"; > > > > + > > > > + vdda-phy-supply = <&vdda_ufs1_core>; > > > > + vdda-pll-supply = <&vdda_ufs1_1p2>; > > > > > > These two properties can be specified in the SoC dtsi file instead of > > > each board variant file. This way we don't have to specify the things > > > that are SoC independent in each board file. The board integrator just > > > has to attach the labels to the right regulator nodes, in this case > > > vdda_ufs1_core and vdda_ufs1_1p2, and then the sdm845.dtsi file will be > > > matched up with the right regulator automatically. It's also nice so > > > that board integrators don't have to know anything besides what > > > regulator goes to what pin on the SoC. > > > > This is an interesting proposal and it feels like we have to consider > > the tradeoffs. > > > > I agree that it would be nice not to have to specify this in every > > single board .dts file, but at the same time what if you've got a > > board that doesn't use UFS? Such a board would bother adding the > > labels "vdda_ufs1_core" and "vdda_ufs1_1p2". This would lead to a > > compile error in the device tree bindings. That seems pretty > > undesirable. > > > > A workaround for this somewhat rare case would be to specify > /delete-property/ on those nodes that aren't used. Unless that can't > even work because the phandle is parsed before properties are deleted? I > haven't tried. Or we could try to have dtc ignore broken phandles in > status = "disabled" nodes or omit them entirely from the dtb so this > isn't a problem. > > Either way, I would push for making it easier for the users of the SoC > to not need to know the SoC internal details too much and rely on the > SoC dtsi file to get it right. From the user perspective it's just a > bunch of pins connected to something. We could also have a 0 volt > "ground" regulator for any grounded/unconnected pins if that helps. It > could be marked as status = "disabled" so that no runtime code is used > while dtc is still happy to have the disabled node with a label. > I dislike the use of the labels "vdda_ufs1_core" as that doesn't tell me which regulator this is actually wired to, without having to jump around in the board dts file. It's annoying, but it's pretty much write-once so it's not a big issue. But I really don't like the idea of having sdm845.dtsi depend on labels specified in the board dtsi. This just means that in order to add a new board I need to figure out the information and the way to specify it is to change a label in the board file. The static configuration here is that vdda-phy-supply is connected to the vdda_ufs1_core pin on the SoC, which is connected to some board specific regulator. If anything I think we should model that intermediate entity, in which case we could move the link between the phy and the pin to the platform dtsi. But I'm fine with us just merging Evan's patch as is. Regards, Bjorn
Quoting Bjorn Andersson (2018-11-21 23:04:12) > On Mon 19 Nov 11:42 PST 2018, Stephen Boyd wrote: > > > > A workaround for this somewhat rare case would be to specify > > /delete-property/ on those nodes that aren't used. Unless that can't > > even work because the phandle is parsed before properties are deleted? I > > haven't tried. Or we could try to have dtc ignore broken phandles in > > status = "disabled" nodes or omit them entirely from the dtb so this > > isn't a problem. > > > > Either way, I would push for making it easier for the users of the SoC > > to not need to know the SoC internal details too much and rely on the > > SoC dtsi file to get it right. From the user perspective it's just a > > bunch of pins connected to something. We could also have a 0 volt > > "ground" regulator for any grounded/unconnected pins if that helps. It > > could be marked as status = "disabled" so that no runtime code is used > > while dtc is still happy to have the disabled node with a label. > > > > I dislike the use of the labels "vdda_ufs1_core" as that doesn't tell me > which regulator this is actually wired to, without having to jump around > in the board dts file. It's annoying, but it's pretty much write-once so > it's not a big issue. > > But I really don't like the idea of having sdm845.dtsi depend on labels > specified in the board dtsi. This just means that in order to add a new > board I need to figure out the information and the way to specify it is > to change a label in the board file. > > > The static configuration here is that vdda-phy-supply is connected to > the vdda_ufs1_core pin on the SoC, which is connected to some board > specific regulator. If anything I think we should model that > intermediate entity, in which case we could move the link between the > phy and the pin to the platform dtsi. > Hmm alright. This is a similar problem that the DT connectors have with phandle remapping through the connector to the actual phandle that is desired. I can think of two solutions. One would be to make a phandle-map binding to remap phandles within the soc node to actually be another phandle. The downside is that we need to make nodes for everything just to remap them. For example: soc { phandle-map { vdda_ufs1_core: vdda-ufs1-core { } }; }; In the SoC dtsi file and then &vdda_ufs1_core { phandle-alias = <&pm8998_ldo19> }; Would be in the board specific dtsi file. The regulator code to fix that up is rather simple, but not generic. It just walks the chain of alias nodes until it doesn't find anything else. diff --git a/drivers/regulator/of_regulator.c b/drivers/regulator/of_regulator.c index 210fc20f7de7..9c1346374351 100644 --- a/drivers/regulator/of_regulator.c +++ b/drivers/regulator/of_regulator.c @@ -432,6 +432,15 @@ static int of_node_match(struct device *dev, const void *data) struct regulator_dev *of_find_regulator_by_node(struct device_node *np) { struct device *dev; + struct device_node *aliased_np; + + do { + aliased_np = of_parse_phandle(np, "phandle-alias", 0); + + if (aliased_np) + np = aliased_np; + + } while (aliased_np); dev = class_find_device(®ulator_class, NULL, np, of_node_match); Another idea would be to have a phandle nexus node that converts phandles into some #cells property. This way, we can make the regulator supply binding parse the cells of the nexus node and figure out that the next specifier after it corresponds to something that needs to be set in the nexus node by the board. soc { soc_regulator: regulator-nexus { #regulator-cells = <1>; #define VDDA_UFS1_CORE 0 }; ufs { vdda-supply = <&soc_regulator VDDA_UFS1_CORE>; }; }; In the SoC dtsi file and then &soc_regulator { regulator-map = <VDDA_UFS1_CORE &pm8998_ldo19> } And then some parsing code in regulator core to remap the cells on the left side to the phandle on the right of the cells. I suppose that makes things sort of awkward and makes the binding look different depending on if the node has the #regulator-cells property or not for the supply binding. Another idea would be to have dts phandle fixups applied somehow when the DT is loaded by the kernel or possibly bootloader or extra efficiently with a compiler change. So then we can alias labels to different labels in the board file. So in the board dtsi file we would have something like soc { phandle-map { vdda-ufs1-core = <&pm8998_ldo19>; }; }; and the SoC dtsi file would have: soc { phandle-map { vdda_ufs1_core: vdda-ufs1-core = <0>; }; }; except I can't get this to compile right now because syntax errors.
diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts index eedfaf8922e2..d5fddea71a85 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts @@ -356,6 +356,20 @@ status = "okay"; }; +&ufshc1 { + status = "okay"; + + vcc-supply = <&vreg_l20a_2p95>; + vcc-max-microamp = <600000>; +}; + +&ufsphy1 { + status = "okay"; + + vdda-phy-supply = <&vdda_ufs1_core>; + vdda-pll-supply = <&vdda_ufs1_1p2>; +}; + &usb_1 { status = "okay"; };