[RFC,v3,00/24] Add RISC-V TCG backend support

Message

Alistair Francis Dec. 8, 2018, 12:46 a.m. UTC

This patch set adds RISC-V backend support to QEMU. This is based on
Michael Clark's original work with extra work ontop.

This has been somewhat tested and can run other architecture softmmu
code. It seems like any OS will eventually hang, but we can run the BIOS
and OS startup code for a number of different operating systems.

I haven't tested linux user support at all yet. I think Michael had that
working reliably though and hopefully my changes haven't broken it. I'll
have to test it before I send a full patchset.

There are still some todos in the code (there are missing instructions
and byte swapping). I think this series will have to be rebased ontop of
Richard's TCG work before merging (although maybe we can get this in and
then work on the rebase).

This branch can be found here:
https://github.com/alistair23/qemu/tree/mainline/alistair/tcg-backend-upstream.next

The working version with Michael's orignal patch and work ontop can be
found here:
https://github.com/alistair23/qemu/tree/mainline/alistair/tcg-backend.next

RFC v3:
 - Update the MAINTAINERS file
 - Enusre that RISC-V 32-bit works
 - More changes based on Richard's feedback and contributions
RFC v2:
 - A large number of changes based on Richard's feedback

Alistair Francis (24):
  elf.h: Add the RISCV ELF magic numbers
  linux-user: Add host dependency for RISC-V 32-bit
  linux-user: Add host dependency for RISC-V 64-bit
  linux-user: riscv: Fix compile failure on riscv32 hosts
  exec: Add RISC-V GCC poison macro
  riscv: Add the tcg-target header file
  riscv: Add the tcg target registers
  riscv: tcg-target: Add support for the constraints
  riscv: tcg-target: Add the immediate encoders
  riscv: tcg-target: Add the instruction emitters
  riscv: tcg-target: Add the relocation functions
  riscv: tcg-target: Add the mov and movi instruction
  riscv: tcg-target: Add the extract instructions
  riscv: tcg-target: Add the out load and store instructions
  riscv: tcg-target: Add the add2 and sub2 instructions
  riscv: tcg-target: Add branch and jump instructions
  riscv: tcg-target: Add slowpath load and store instructions
  riscv: tcg-target: Add direct load and store instructions
  riscv: tcg-target: Add the out op decoder
  riscv: tcg-target: Add the prologue generation and register the JIT
  riscv: tcg-target: Add the target init code
  tcg: Add RISC-V cpu signal handler
  dias: Add RISC-V support
  configure: Add support for building RISC-V host

 MAINTAINERS                       |    3 +
 accel/tcg/user-exec.c             |   75 ++
 configure                         |   12 +-
 disas.c                           |   10 +-
 include/elf.h                     |   55 +
 include/exec/poison.h             |    1 +
 linux-user/host/riscv32/hostdep.h |   11 +
 linux-user/host/riscv64/hostdep.h |   11 +
 linux-user/riscv/target_syscall.h |    5 +
 tcg/riscv/tcg-target.h            |  175 +++
 tcg/riscv/tcg-target.inc.c        | 1927 +++++++++++++++++++++++++++++
 11 files changed, 2281 insertions(+), 4 deletions(-)
 create mode 100644 linux-user/host/riscv32/hostdep.h
 create mode 100644 linux-user/host/riscv64/hostdep.h
 create mode 100644 tcg/riscv/tcg-target.h
 create mode 100644 tcg/riscv/tcg-target.inc.c

Comments

[e-mail] Dec. 8, 2018, 2:13 a.m. UTC | #1

Patchew URL: https://patchew.org/QEMU/[e-mail]/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: [e-mail]
Subject: [Qemu-devel] [RFC v3 00/24]  Add RISC-V TCG backend support
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
bd18a68 configure: Add support for building RISC-V host
4b6694e dias: Add RISC-V support
75231f4 tcg: Add RISC-V cpu signal handler
d11076a riscv: tcg-target: Add the target init code
7a29026 riscv: tcg-target: Add the prologue generation and register the JIT
cfbf3a4 riscv: tcg-target: Add the out op decoder
c9b64db riscv: tcg-target: Add direct load and store instructions
b3bce92 riscv: tcg-target: Add slowpath load and store instructions
f638bf5 riscv: tcg-target: Add branch and jump instructions
aad70de riscv: tcg-target: Add the add2 and sub2 instructions
b2aad81 riscv: tcg-target: Add the out load and store instructions
9e4ea2d riscv: tcg-target: Add the extract instructions
d1b0709 riscv: tcg-target: Add the mov and movi instruction
f8005d6 riscv: tcg-target: Add the relocation functions
451a32e riscv: tcg-target: Add the instruction emitters
8888c7f riscv: tcg-target: Add the immediate encoders
b6ab31a riscv: tcg-target: Add support for the constraints
ae54474 riscv: Add the tcg target registers
2fe9951 riscv: Add the tcg-target header file
291d809 exec: Add RISC-V GCC poison macro
eb8cb60 linux-user: riscv: Fix compile failure on riscv32 hosts
ba54a72 linux-user: Add host dependency for RISC-V 64-bit
f7775fe linux-user: Add host dependency for RISC-V 32-bit
faa86e4 elf.h: Add the RISCV ELF magic numbers

=== OUTPUT BEGIN ===
Checking PATCH 1/24: elf.h: Add the RISCV ELF magic numbers...
Checking PATCH 2/24: linux-user: Add host dependency for RISC-V 32-bit...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#24: 
new file mode 100644

total: 0 errors, 1 warnings, 18 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 3/24: linux-user: Add host dependency for RISC-V 64-bit...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#24: 
new file mode 100644

total: 0 errors, 1 warnings, 18 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 4/24: linux-user: riscv: Fix compile failure on riscv32 hosts...
WARNING: architecture specific defines should be avoided
#23: FILE: linux-user/riscv/target_syscall.h:51:
+#if !defined(__NR__llseek) && !defined(__NR_lseek)

total: 0 errors, 1 warnings, 11 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 5/24: exec: Add RISC-V GCC poison macro...
Checking PATCH 6/24: riscv: Add the tcg-target header file...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#24: 
new file mode 100644

WARNING: architecture specific defines should be avoided
#56: FILE: tcg/riscv/tcg-target.h:28:
+#if __riscv_xlen == 32

total: 0 errors, 2 warnings, 182 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 7/24: riscv: Add the tcg target registers...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#12: 
new file mode 100644

total: 0 errors, 1 warnings, 118 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 8/24: riscv: tcg-target: Add support for the constraints...
Checking PATCH 9/24: riscv: tcg-target: Add the immediate encoders...
Checking PATCH 10/24: riscv: tcg-target: Add the instruction emitters...
Checking PATCH 11/24: riscv: tcg-target: Add the relocation functions...
Checking PATCH 12/24: riscv: tcg-target: Add the mov and movi instruction...
Checking PATCH 13/24: riscv: tcg-target: Add the extract instructions...
Checking PATCH 14/24: riscv: tcg-target: Add the out load and store instructions...
Checking PATCH 15/24: riscv: tcg-target: Add the add2 and sub2 instructions...
Checking PATCH 16/24: riscv: tcg-target: Add branch and jump instructions...
Checking PATCH 17/24: riscv: tcg-target: Add slowpath load and store instructions...
Checking PATCH 18/24: riscv: tcg-target: Add direct load and store instructions...
ERROR: spaces required around that '*' (ctx:WxV)
#73: FILE: tcg/riscv/tcg-target.inc.c:1190:
+    tcg_insn_unit *label_ptr[1];
                   ^

ERROR: spaces required around that '*' (ctx:WxV)
#144: FILE: tcg/riscv/tcg-target.inc.c:1261:
+    tcg_insn_unit *label_ptr[1];
                   ^

total: 2 errors, 0 warnings, 161 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 19/24: riscv: tcg-target: Add the out op decoder...
Checking PATCH 20/24: riscv: tcg-target: Add the prologue generation and register the JIT...
Checking PATCH 21/24: riscv: tcg-target: Add the target init code...
Checking PATCH 22/24: tcg: Add RISC-V cpu signal handler...
Checking PATCH 23/24: dias: Add RISC-V support...
WARNING: architecture specific defines should be avoided
#22: FILE: disas.c:526:
+#if defined(_ILP32) || (__riscv_xlen == 32)

total: 0 errors, 1 warnings, 16 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 24/24: configure: Add support for building RISC-V host...
=== OUTPUT END ===

Test command exited with code: 1


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