| Message ID | 20181216092524.20337-1-harald@ccbib.org (mailing list archive) |
|---|---|
| State | Mainlined, archived |
| Commit | 7e345d25c796abc8561786baaf59f30bc082ef1f |
| Headers | show |
| Series | ARM: dts: sun4i-a10: Add PMU node | expand |
Hi! On Sun, Dec 16, 2018 at 09:25:24AM +0000, Harald Geyer wrote: > This is necessary to use 'perf' for cache profiling etc. > Tested on cubieboard with 'perf stat echo foo'. > > Signed-off-by: Harald Geyer <harald@ccbib.org> Queued for 4.22, thanks > --- > arch/arm/boot/dts/sun4i-a10.dtsi | 5 +++++ > 1 file changed, 5 insertions(+) > > While looking into this, I noticed that the dtsi files for the allwinner > SoCs have no information about caches in them. Is this on purpose? No, it's just that no one did it so far. Maxime
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 5d46bb0139fa..a2fb473cbb9d 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -184,6 +184,11 @@ status = "disabled"; }; + pmu { + compatible = "arm,cortex-a8-pmu"; + interrupts = <3>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>;
This is necessary to use 'perf' for cache profiling etc. Tested on cubieboard with 'perf stat echo foo'. Signed-off-by: Harald Geyer <harald@ccbib.org> --- arch/arm/boot/dts/sun4i-a10.dtsi | 5 +++++ 1 file changed, 5 insertions(+) While looking into this, I noticed that the dtsi files for the allwinner SoCs have no information about caches in them. Is this on purpose?