| Message ID | 1544780260-27590-7-git-send-email-fabrizio.castro@bp.renesas.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 62c0056f1c3eb15d6f40c2b958e0e023d5845852 |
| Delegated to: | Simon Horman |
| Headers | show |
| Series | Add more support for the RZ/G2E | expand |
On Fri, Dec 14, 2018 at 09:37:29AM +0000, Fabrizio Castro wrote: > Add the device nodes for all MSIOF SPI controllers on RZ/G2E SoC. > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
On Fri, Dec 14, 2018 at 10:38 AM Fabrizio Castro <fabrizio.castro@bp.renesas.com> wrote: > Add the device nodes for all MSIOF SPI controllers on RZ/G2E SoC. > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
Hello! On 12/14/2018 12:37 PM, Fabrizio Castro wrote: > Add the device nodes for all MSIOF SPI controllers on RZ/G2E SoC. > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > --- > arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 62 +++++++++++++++++++++++++++++++ > 1 file changed, 62 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > index 9532d29..9bd66b1 100644 > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > @@ -855,6 +855,68 @@ > status = "disabled"; > }; > > + msiof0: spi@e6e90000 { > + compatible = "renesas,msiof-r8a774c0", > + "renesas,rcar-gen3-msiof"; > + reg = <0 0xe6e90000 0 0x0064>; Do we really need the leading zeros in the size cells? > + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD 211>; > + dmas = <&dmac1 0x41>, <&dmac1 0x40>, > + <&dmac2 0x41>, <&dmac2 0x40>; > + dma-names = "tx", "rx", "tx", "rx"; > + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; > + resets = <&cpg 211>; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + }; [...] Same question for the other instances of MSIOF. MBR, Sergei
Hello Sergei, Thank you for your feedback! > From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > Sent: 17 December 2018 16:27 > To: Fabrizio Castro <fabrizio.castro@bp.renesas.com>; Rob Herring <robh+dt@kernel.org>; Geert Uytterhoeven > Subject: Re: [PATCH 06/17] arm64: dts: renesas: r8a774c0: Add MSIOF nodes > > Hello! > > On 12/14/2018 12:37 PM, Fabrizio Castro wrote: > > > Add the device nodes for all MSIOF SPI controllers on RZ/G2E SoC. > > > > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> > > --- > > arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 62 +++++++++++++++++++++++++++++++ > > 1 file changed, 62 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > > index 9532d29..9bd66b1 100644 > > --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi > > @@ -855,6 +855,68 @@ > > status = "disabled"; > > }; > > > > +msiof0: spi@e6e90000 { > > +compatible = "renesas,msiof-r8a774c0", > > + "renesas,rcar-gen3-msiof"; > > +reg = <0 0xe6e90000 0 0x0064>; > > Do we really need the leading zeros in the size cells? We don't, I just kept it consistent with the same definitions for the other platforms. Do you want me to send a v2 for this? > > > +interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; > > +clocks = <&cpg CPG_MOD 211>; > > +dmas = <&dmac1 0x41>, <&dmac1 0x40>, > > + <&dmac2 0x41>, <&dmac2 0x40>; > > +dma-names = "tx", "rx", "tx", "rx"; > > +power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; > > +resets = <&cpg 211>; > > +#address-cells = <1>; > > +#size-cells = <0>; > > +status = "disabled"; > > +}; > [...] > > Same question for the other instances of MSIOF. Same answer applies for the other instances. Thanks, Fab > > MBR, Sergei [https://www2.renesas.eu/media/email/unicef.jpg] This Christmas, instead of sending out cards, Renesas Electronics Europe have decided to support Unicef with a donation. For further details click here<https://www.unicef.org/> to find out about the valuable work they do, helping children all over the world. We would like to take this opportunity to wish you a Merry Christmas and a prosperous New Year. Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
On 12/17/2018 07:36 PM, Fabrizio Castro wrote: [...] >>> Add the device nodes for all MSIOF SPI controllers on RZ/G2E SoC. >>> >>> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> >>> --- >>> arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 62 +++++++++++++++++++++++++++++++ >>> 1 file changed, 62 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi >>> index 9532d29..9bd66b1 100644 >>> --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi >>> +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi >>> @@ -855,6 +855,68 @@ >>> status = "disabled"; >>> }; >>> >>> +msiof0: spi@e6e90000 { >>> +compatible = "renesas,msiof-r8a774c0", >>> + "renesas,rcar-gen3-msiof"; >>> +reg = <0 0xe6e90000 0 0x0064>; >> >> Do we really need the leading zeros in the size cells? > > We don't, I just kept it consistent with the same definitions for the other platforms. > Do you want me to send a v2 for this? Ah, consistency is good. Keep it then. :-) MBR, Sergei
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 9532d29..9bd66b1 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -855,6 +855,68 @@ status = "disabled"; }; + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a774c0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a774c0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a774c0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a774c0", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a774c0", "renesas,rcar-gen3-sdhi";
Add the device nodes for all MSIOF SPI controllers on RZ/G2E SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 62 +++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+)