| Message ID | cover.1545246859.git.alistair.francis@wdc.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add RISC-V TCG backend support | expand |
On 12/19/18 11:16 AM, Alistair Francis wrote: > This patch set adds RISC-V backend support to QEMU. This is based on > Michael Clark's original work with extra work on top. > > This has been somewhat tested and can run other architecture softmmu > code. It seems that any complex OS will eventually hang, but we can > run the BIOS and OS startup code for a number of different operating > systems. > > I haven't tested linux user support at all yet. I think Michael had that > working reliably though and hopefully my changes haven't broken it. > > There are still some todos in the code (there are missing instructions > and byte swapping) but these should assert instead of generating invalid > code. Queued to tcg-next, with the extrh fix. Some of those todos are no longer todos, since e.g. bswap is now optional. Those asserts should never fire (as a good assert should do, I suppose). The missing instructions are only for riscv32, which afaik is just now making its way to glibc. So a chroot complete enough to build qemu is a ways away. I'm ok with leaving that incomplete for now. r~
On Wed, Dec 19, 2018 at 10:07 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > On 12/19/18 11:16 AM, Alistair Francis wrote: > > This patch set adds RISC-V backend support to QEMU. This is based on > > Michael Clark's original work with extra work on top. > > > > This has been somewhat tested and can run other architecture softmmu > > code. It seems that any complex OS will eventually hang, but we can > > run the BIOS and OS startup code for a number of different operating > > systems. > > > > I haven't tested linux user support at all yet. I think Michael had that > > working reliably though and hopefully my changes haven't broken it. > > > > There are still some todos in the code (there are missing instructions > > and byte swapping) but these should assert instead of generating invalid > > code. > > Queued to tcg-next, with the extrh fix. Thanks Richard! > > Some of those todos are no longer todos, since e.g. bswap is now optional. > Those asserts should never fire (as a good assert should do, I suppose). > > The missing instructions are only for riscv32, which afaik is just now making > its way to glibc. So a chroot complete enough to build qemu is a ways away. > I'm ok with leaving that incomplete for now. > > > r~
On Thu, 20 Dec 2018 09:20:05 PST (-0800), alistair23@gmail.com wrote: > On Wed, Dec 19, 2018 at 10:07 PM Richard Henderson > <richard.henderson@linaro.org> wrote: >> >> On 12/19/18 11:16 AM, Alistair Francis wrote: >> > This patch set adds RISC-V backend support to QEMU. This is based on >> > Michael Clark's original work with extra work on top. >> > >> > This has been somewhat tested and can run other architecture softmmu >> > code. It seems that any complex OS will eventually hang, but we can >> > run the BIOS and OS startup code for a number of different operating >> > systems. >> > >> > I haven't tested linux user support at all yet. I think Michael had that >> > working reliably though and hopefully my changes haven't broken it. >> > >> > There are still some todos in the code (there are missing instructions >> > and byte swapping) but these should assert instead of generating invalid >> > code. >> >> Queued to tcg-next, with the extrh fix. > > Thanks Richard! Sounds good to me. I'm still attempting to collect the RISC-V patches to get a PR out, a few things came up but I should have time now. This was the biggest patch set, so it should be a lot easier now. Thanks for picking this up! >> Some of those todos are no longer todos, since e.g. bswap is now optional. >> Those asserts should never fire (as a good assert should do, I suppose). >> >> The missing instructions are only for riscv32, which afaik is just now making >> its way to glibc. So a chroot complete enough to build qemu is a ways away. >> I'm ok with leaving that incomplete for now. We've decided to delay the rv32i glibc port until after the next glibc release, which is targeted for the beginning of February. glibc should freeze at the end of the year, at which point we're going to do a rv32i glibc prerelease and try to build a proper userspace with the theory being that we'll shake out ABI bugs that way.
On Thu, Dec 20, 2018 at 10:45 AM Palmer Dabbelt <palmer@sifive.com> wrote: > > On Thu, 20 Dec 2018 09:20:05 PST (-0800), alistair23@gmail.com wrote: > > On Wed, Dec 19, 2018 at 10:07 PM Richard Henderson > > <richard.henderson@linaro.org> wrote: > >> > >> On 12/19/18 11:16 AM, Alistair Francis wrote: > >> > This patch set adds RISC-V backend support to QEMU. This is based on > >> > Michael Clark's original work with extra work on top. > >> > > >> > This has been somewhat tested and can run other architecture softmmu > >> > code. It seems that any complex OS will eventually hang, but we can > >> > run the BIOS and OS startup code for a number of different operating > >> > systems. > >> > > >> > I haven't tested linux user support at all yet. I think Michael had that > >> > working reliably though and hopefully my changes haven't broken it. > >> > > >> > There are still some todos in the code (there are missing instructions > >> > and byte swapping) but these should assert instead of generating invalid > >> > code. > >> > >> Queued to tcg-next, with the extrh fix. > > > > Thanks Richard! > > Sounds good to me. I'm still attempting to collect the RISC-V patches to get a > PR out, a few things came up but I should have time now. This was the biggest > patch set, so it should be a lot easier now. > > Thanks for picking this up! > > >> Some of those todos are no longer todos, since e.g. bswap is now optional. > >> Those asserts should never fire (as a good assert should do, I suppose). > >> > >> The missing instructions are only for riscv32, which afaik is just now making > >> its way to glibc. So a chroot complete enough to build qemu is a ways away. > >> I'm ok with leaving that incomplete for now. > > We've decided to delay the rv32i glibc port until after the next glibc release, > which is targeted for the beginning of February. glibc should freeze at the > end of the year, at which point we're going to do a rv32i glibc prerelease and > try to build a proper userspace with the theory being that we'll shake out ABI > bugs that way. Yocto/OE has full support for building 32-bit userspaces with the latest 32-bit glibc patchset so that is probably a good place to start testing. It even runs QEMU! Alistair
Patchew URL: https://patchew.org/QEMU/cover.1545246859.git.alistair.francis@wdc.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: cover.1545246859.git.alistair.francis@wdc.com
Type: series
Subject: [Qemu-devel] [PATCH v2 00/23] Add RISC-V TCG backend support
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
2236221 configure: Add support for building RISC-V host
e990378 dias: Add RISC-V support
713b47c tcg: Add RISC-V cpu signal handler
8ec51ee riscv: tcg-target: Add the target init code
3feff31 riscv: tcg-target: Add the prologue generation and register the JIT
702fdc0 riscv: tcg-target: Add the out op decoder
ed66ad3 riscv: tcg-target: Add direct load and store instructions
fd97412 riscv: tcg-target: Add slowpath load and store instructions
5e6bb90 riscv: tcg-target: Add branch and jump instructions
a066182 riscv: tcg-target: Add the add2 and sub2 instructions
8192923 riscv: tcg-target: Add the out load and store instructions
65e8bfc riscv: tcg-target: Add the extract instructions
37fba48 riscv: tcg-target: Add the mov and movi instruction
e015e10 riscv: tcg-target: Add the relocation functions
67927da riscv: tcg-target: Add the instruction emitters
def52f9 riscv: tcg-target: Add the immediate encoders
db3a876 riscv: tcg-target: Add support for the constraints
472711b riscv: Add the tcg target registers
cb5271e riscv: Add the tcg-target header file
c053c44 exec: Add RISC-V GCC poison macro
a4660da linux-user: Add host dependency for RISC-V 64-bit
cec4a16 linux-user: Add host dependency for RISC-V 32-bit
52105f5 elf.h: Add the RISCV ELF magic numbers
=== OUTPUT BEGIN ===
Checking PATCH 1/23: elf.h: Add the RISCV ELF magic numbers...
Checking PATCH 2/23: linux-user: Add host dependency for RISC-V 32-bit...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#24:
new file mode 100644
total: 0 errors, 1 warnings, 18 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 3/23: linux-user: Add host dependency for RISC-V 64-bit...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#24:
new file mode 100644
total: 0 errors, 1 warnings, 18 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 4/23: exec: Add RISC-V GCC poison macro...
Checking PATCH 5/23: riscv: Add the tcg-target header file...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#40:
new file mode 100644
WARNING: architecture specific defines should be avoided
#72: FILE: tcg/riscv/tcg-target.h:28:
+#if __riscv_xlen == 32
total: 0 errors, 2 warnings, 199 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 6/23: riscv: Add the tcg target registers...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#12:
new file mode 100644
total: 0 errors, 1 warnings, 118 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 7/23: riscv: tcg-target: Add support for the constraints...
Checking PATCH 8/23: riscv: tcg-target: Add the immediate encoders...
Checking PATCH 9/23: riscv: tcg-target: Add the instruction emitters...
Checking PATCH 10/23: riscv: tcg-target: Add the relocation functions...
Checking PATCH 11/23: riscv: tcg-target: Add the mov and movi instruction...
Checking PATCH 12/23: riscv: tcg-target: Add the extract instructions...
Checking PATCH 13/23: riscv: tcg-target: Add the out load and store instructions...
Checking PATCH 14/23: riscv: tcg-target: Add the add2 and sub2 instructions...
WARNING: Block comments use a leading /* on a separate line
#30: FILE: tcg/riscv/tcg-target.inc.c:710:
+ /* If we have a negative constant such that negating it would
WARNING: Block comments use * on subsequent lines
#31: FILE: tcg/riscv/tcg-target.inc.c:711:
+ /* If we have a negative constant such that negating it would
+ make the high part zero, we can (usually) eliminate one insn. */
WARNING: Block comments use a trailing */ on a separate line
#31: FILE: tcg/riscv/tcg-target.inc.c:711:
+ make the high part zero, we can (usually) eliminate one insn. */
WARNING: Block comments use a leading /* on a separate line
#38: FILE: tcg/riscv/tcg-target.inc.c:718:
+ /* By operating on the high part first, we get to use the final
WARNING: Block comments use * on subsequent lines
#39: FILE: tcg/riscv/tcg-target.inc.c:719:
+ /* By operating on the high part first, we get to use the final
+ carry operation to move back from the temporary. */
WARNING: Block comments use a trailing */ on a separate line
#39: FILE: tcg/riscv/tcg-target.inc.c:719:
+ carry operation to move back from the temporary. */
total: 0 errors, 6 warnings, 58 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 15/23: riscv: tcg-target: Add branch and jump instructions...
Checking PATCH 16/23: riscv: tcg-target: Add slowpath load and store instructions...
WARNING: Block comments use a leading /* on a separate line
#46: FILE: tcg/riscv/tcg-target.inc.c:925:
+/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
WARNING: Block comments use a leading /* on a separate line
#68: FILE: tcg/riscv/tcg-target.inc.c:947:
+/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
WARNING: Block comments use a leading /* on a separate line
#173: FILE: tcg/riscv/tcg-target.inc.c:1052:
+ /* TODO: Move this out of line
total: 0 errors, 3 warnings, 259 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 17/23: riscv: tcg-target: Add direct load and store instructions...
ERROR: spaces required around that '*' (ctx:WxV)
#74: FILE: tcg/riscv/tcg-target.inc.c:1209:
+ tcg_insn_unit *label_ptr[1];
^
ERROR: spaces required around that '*' (ctx:WxV)
#145: FILE: tcg/riscv/tcg-target.inc.c:1280:
+ tcg_insn_unit *label_ptr[1];
^
total: 2 errors, 0 warnings, 161 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 18/23: riscv: tcg-target: Add the out op decoder...
Checking PATCH 19/23: riscv: tcg-target: Add the prologue generation and register the JIT...
Checking PATCH 20/23: riscv: tcg-target: Add the target init code...
Checking PATCH 21/23: tcg: Add RISC-V cpu signal handler...
WARNING: Block comments use a leading /* on a separate line
#29: FILE: accel/tcg/user-exec.c:585:
+ /* Detect store by reading the instruction at the program
WARNING: Block comments use * on subsequent lines
#30: FILE: accel/tcg/user-exec.c:586:
+ /* Detect store by reading the instruction at the program
+ counter. Note: we currently only generate 32-bit
WARNING: Block comments use a trailing */ on a separate line
#31: FILE: accel/tcg/user-exec.c:587:
+ instructions so we thus only detect 32-bit stores */
total: 0 errors, 3 warnings, 81 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 22/23: dias: Add RISC-V support...
WARNING: architecture specific defines should be avoided
#22: FILE: disas.c:526:
+#if defined(_ILP32) || (__riscv_xlen == 32)
total: 0 errors, 1 warnings, 16 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 23/23: configure: Add support for building RISC-V host...
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/cover.1545246859.git.alistair.francis@wdc.com/testing.checkpatch/?type=message.
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