| Message ID | 20190109213147.16851-1-daniele.ceraolospurio@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: drop DPF code for gen8+ | expand |
Quoting Daniele Ceraolo Spurio (2019-01-09 21:31:47) > The only gen8+ platform that has the feature is BDW, but we don't define > the feature flag on any BDW platform and we only have partial support in > the gen8 path (irq enabling code, but no handler). > The only thing we could do in the irq handler is report the error > to userspace, but no one asked/cared about that since BDW was > released so it is relatively safe to assume that even if we added the > message no one would look at it. Just drop the dead code from the > driver instead. > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> I'm not volunteering myself to add support, and should anyone be the code removed here would be trivial to reimplement and a mere fraction of the code required. Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
Quoting Daniele Ceraolo Spurio (2019-01-09 21:31:47) > The only gen8+ platform that has the feature is BDW, but we don't define > the feature flag on any BDW platform and we only have partial support in > the gen8 path (irq enabling code, but no handler). > The only thing we could do in the irq handler is report the error > to userspace, but no one asked/cared about that since BDW was > released so it is relatively safe to assume that even if we added the > message no one would look at it. Just drop the dead code from the > driver instead. > > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> And pushed, thanks for the tidy up. -Chris
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index fbb094ecf6c9..1f5d756c76cf 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -4173,9 +4173,6 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT }; - if (HAS_L3_DPF(dev_priv)) - gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; - dev_priv->pm_ier = 0x0; dev_priv->pm_imr = ~dev_priv->pm_ier; GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 13c6c579ec7a..f5fa8242caaa 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -2267,14 +2267,10 @@ static int logical_ring_init(struct intel_engine_cs *engine) int logical_render_ring_init(struct intel_engine_cs *engine) { - struct drm_i915_private *dev_priv = engine->i915; int ret; logical_ring_setup(engine); - if (HAS_L3_DPF(dev_priv)) - engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; - /* Override some for render ring. */ engine->init_context = gen8_init_rcs_context; engine->emit_flush = gen8_emit_flush_render;
The only gen8+ platform that has the feature is BDW, but we don't define the feature flag on any BDW platform and we only have partial support in the gen8 path (irq enabling code, but no handler). The only thing we could do in the irq handler is report the error to userspace, but no one asked/cared about that since BDW was released so it is relatively safe to assume that even if we added the message no one would look at it. Just drop the dead code from the driver instead. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 3 --- drivers/gpu/drm/i915/intel_lrc.c | 4 ---- 2 files changed, 7 deletions(-)