| Message ID | 20190118145730.22227-2-paul.kocialkowski@bootlin.com (mailing list archive) |
|---|---|
| State | Mainlined, archived |
| Commit | 5949bc5602ccd88161982e646432944eb318fa6e |
| Headers | show |
| Series | [1/2] ARM: dts: sun4i: Add support for the C1 SRAM region with the SRAM controller | expand |
On Fri, Jan 18, 2019 at 03:57:30PM +0100, Paul Kocialkowski wrote: > This adds nodes for the Video Engine and the associated reserved memory > for the A10. Up to 96 MiB of memory are dedicated to the CMA pool. > > The VPU can only map the first 256 MiB of DRAM, so the reserved memory > pool has to be located in that area. Following Allwinner's decision in > downstream software, the last 96 MiB of the first 256 MiB of RAM are > reserved for this purpose. > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Applied both, thanks Maxime
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index c3a74024ca0f..73c3ac42095f 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -189,6 +189,21 @@ interrupts = <3>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ + default-pool { + compatible = "shared-dma-pool"; + size = <0x6000000>; + alloc-ranges = <0x4a000000 0x6000000>; + reusable; + linux,cma-default; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -412,6 +427,17 @@ }; }; + video-codec@1c0e000 { + compatible = "allwinner,sun4i-a10-video-engine"; + reg = <0x01c0e000 0x1000>; + clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_VE>; + interrupts = <53>; + allwinner,sram = <&ve_sram 1>; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun4i-a10-mmc"; reg = <0x01c0f000 0x1000>;
This adds nodes for the Video Engine and the associated reserved memory for the A10. Up to 96 MiB of memory are dedicated to the CMA pool. The VPU can only map the first 256 MiB of DRAM, so the reserved memory pool has to be located in that area. Following Allwinner's decision in downstream software, the last 96 MiB of the first 256 MiB of RAM are reserved for this purpose. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> --- arch/arm/boot/dts/sun4i-a10.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+)