diff mbox series

[v2,2/2] drm/msm: Cleanup A6XX opp-level reading

Message ID 20190116184623.77136-2-dianders@chromium.org (mailing list archive)
State New, archived
Headers show
Series [v2,1/2] drm/msm: Fix A6XX support for opp-level | expand

Commit Message

Doug Anderson Jan. 16, 2019, 6:46 p.m. UTC
The patch ("OPP: Add support for parsing the 'opp-level' property")
adds an API enabling a cleaner way to read the opp-level.  Let's use
the new API.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
---
Obviously this can't land until we have a tree that contains the patch
adding the API.  I believe that means we'll want to target this patch
for 5.2.  Luckily it's fine to wait since this patch has no functional
changes--it's all cleanup.

Changes in v2:
- Split into two patches to facilitate landing.

 drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 17 ++++++-----------
 1 file changed, 6 insertions(+), 11 deletions(-)

Comments

kernel test robot Jan. 22, 2019, 2:21 a.m. UTC | #1
Hi Douglas,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on v5.0-rc2]
[also build test ERROR on next-20190116]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Douglas-Anderson/drm-msm-Fix-A6XX-support-for-opp-level/20190118-042538
config: arm-imx_v6_v7_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 8.2.0-11) 8.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=8.2.0 make.cross ARCH=arm 

All errors (new ones prefixed by >>):

   drivers/gpu/drm/msm/adreno/a6xx_gmu.c: In function 'a6xx_gmu_get_arc_level':
>> drivers/gpu/drm/msm/adreno/a6xx_gmu.c:944:8: error: implicit declaration of function 'dev_pm_opp_get_level'; did you mean 'dev_pm_opp_get_freq'? [-Werror=implicit-function-declaration]
     val = dev_pm_opp_get_level(opp);
           ^~~~~~~~~~~~~~~~~~~~
           dev_pm_opp_get_freq
   cc1: some warnings being treated as errors

vim +944 drivers/gpu/drm/msm/adreno/a6xx_gmu.c

   929	
   930	/* Return the 'arc-level' for the given frequency */
   931	static unsigned int a6xx_gmu_get_arc_level(struct device *dev,
   932						   unsigned long freq)
   933	{
   934		struct dev_pm_opp *opp;
   935		unsigned int val;
   936	
   937		if (!freq)
   938			return 0;
   939	
   940		opp = dev_pm_opp_find_freq_exact(dev, freq, true);
   941		if (IS_ERR(opp))
   942			return 0;
   943	
 > 944		val = dev_pm_opp_get_level(opp);
   945	
   946		dev_pm_opp_put(opp);
   947	
   948		return val;
   949	}
   950	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
Doug Anderson March 18, 2019, 8:38 p.m. UTC | #2
Hi,

On Wed, Jan 16, 2019 at 10:46 AM Douglas Anderson <dianders@chromium.org> wrote:
>
> The patch ("OPP: Add support for parsing the 'opp-level' property")
> adds an API enabling a cleaner way to read the opp-level.  Let's use
> the new API.
>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
> ---
> Obviously this can't land until we have a tree that contains the patch
> adding the API.  I believe that means we'll want to target this patch
> for 5.2.  Luckily it's fine to wait since this patch has no functional
> changes--it's all cleanup.
>
> Changes in v2:
> - Split into two patches to facilitate landing.
>
>  drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 17 ++++++-----------
>  1 file changed, 6 insertions(+), 11 deletions(-)

FWIW I think this patch is ready to land any time.  That commit
5b93ac542301 ("OPP: Add support for parsing the 'opp-level' property")
is now in linux/master.


-Doug
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index ce1b3cc4bf6d..900f18dc1577 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -928,25 +928,20 @@  static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
 }
 
 /* Return the 'arc-level' for the given frequency */
-static u32 a6xx_gmu_get_arc_level(struct device *dev, unsigned long freq)
+static unsigned int a6xx_gmu_get_arc_level(struct device *dev,
+					   unsigned long freq)
 {
 	struct dev_pm_opp *opp;
-	struct device_node *np;
-	u32 val = 0;
+	unsigned int val;
 
 	if (!freq)
 		return 0;
 
-	opp  = dev_pm_opp_find_freq_exact(dev, freq, true);
+	opp = dev_pm_opp_find_freq_exact(dev, freq, true);
 	if (IS_ERR(opp))
 		return 0;
 
-	np = dev_pm_opp_get_of_node(opp);
-
-	if (np) {
-		of_property_read_u32(np, "opp-level", &val);
-		of_node_put(np);
-	}
+	val = dev_pm_opp_get_level(opp);
 
 	dev_pm_opp_put(opp);
 
@@ -982,7 +977,7 @@  static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes,
 	/* Construct a vote for each frequency */
 	for (i = 0; i < freqs_count; i++) {
 		u8 pindex = 0, sindex = 0;
-		u32 level = a6xx_gmu_get_arc_level(dev, freqs[i]);
+		unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]);
 
 		/* Get the primary index that matches the arc level */
 		for (j = 0; j < pri_count; j++) {