diff mbox series

[10/13] arm64: dts: qcom: qcs404: Add HFPLL node

Message ID 1545039990-19984-11-git-send-email-jorge.ramirez-ortiz@linaro.org (mailing list archive)
State Not Applicable, archived
Headers show
Series Support CPU frequency scaling on QCS404 | expand

Commit Message

Jorge Ramirez-Ortiz Dec. 17, 2018, 9:46 a.m. UTC
The high frequency pll functionality is required to enable CPU
frequency scaling operation.

Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Stephen Boyd Dec. 17, 2018, 7:39 p.m. UTC | #1
Quoting Jorge Ramirez-Ortiz (2018-12-17 01:46:27)
> The high frequency pll functionality is required to enable CPU
> frequency scaling operation.
> 
> Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> ---
>  arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index 4594fea7..ec3f6c7 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -375,6 +375,15 @@
>                         #mbox-cells = <1>;
>                 };
>  
> +               apcs_hfpll: clock-controller@0b016000 {

Drop leading 0 on unit address please.

> +                       compatible = "qcom,hfpll";
> +                       reg = <0x0b016000 0x30>;

Wow that is small!

> +                       #clock-cells = <0>;
> +                       clock-output-names = "apcs_hfpll";
> +                       clocks = <&xo_board>;
> +                       clock-names = "xo";
> +               };
> +
Bjorn Andersson Jan. 17, 2019, 6:38 a.m. UTC | #2
On Mon 17 Dec 11:39 PST 2018, Stephen Boyd wrote:

> Quoting Jorge Ramirez-Ortiz (2018-12-17 01:46:27)
> > The high frequency pll functionality is required to enable CPU
> > frequency scaling operation.
> > 
> > Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> > Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> > Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> > ---
> >  arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> > index 4594fea7..ec3f6c7 100644
> > --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> > @@ -375,6 +375,15 @@
> >                         #mbox-cells = <1>;
> >                 };
> >  
> > +               apcs_hfpll: clock-controller@0b016000 {
> 
> Drop leading 0 on unit address please.
> 
> > +                       compatible = "qcom,hfpll";
> > +                       reg = <0x0b016000 0x30>;
> 
> Wow that is small!
> 

I double checked and it's actually 0x34, but the last register is
protected.

Regards,
Bjorn

> > +                       #clock-cells = <0>;
> > +                       clock-output-names = "apcs_hfpll";
> > +                       clocks = <&xo_board>;
> > +                       clock-names = "xo";
> > +               };
> > +
Stephen Boyd Jan. 22, 2019, 6:49 p.m. UTC | #3
Quoting Bjorn Andersson (2019-01-16 22:38:04)
> On Mon 17 Dec 11:39 PST 2018, Stephen Boyd wrote:
> 
> > Quoting Jorge Ramirez-Ortiz (2018-12-17 01:46:27)
> > > The high frequency pll functionality is required to enable CPU
> > > frequency scaling operation.
> > > 
> > > Co-developed-by: Niklas Cassel <niklas.cassel@linaro.org>
> > > Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
> > > Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
> > > ---
> > >  arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +++++++++
> > >  1 file changed, 9 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> > > index 4594fea7..ec3f6c7 100644
> > > --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> > > @@ -375,6 +375,15 @@
> > >                         #mbox-cells = <1>;
> > >                 };
> > >  
> > > +               apcs_hfpll: clock-controller@0b016000 {
> > 
> > Drop leading 0 on unit address please.
> > 
> > > +                       compatible = "qcom,hfpll";
> > > +                       reg = <0x0b016000 0x30>;
> > 
> > Wow that is small!
> > 
> 
> I double checked and it's actually 0x34, but the last register is
> protected.
> 

Ok, so then it should be 0x34? I don't think we've left out protected
registers from the size before.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 4594fea7..ec3f6c7 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -375,6 +375,15 @@ 
 			#mbox-cells = <1>;
 		};
 
+		apcs_hfpll: clock-controller@0b016000 {
+			compatible = "qcom,hfpll";
+			reg = <0x0b016000 0x30>;
+			#clock-cells = <0>;
+			clock-output-names = "apcs_hfpll";
+			clocks = <&xo_board>;
+			clock-names = "xo";
+		};
+
 		timer@b120000 {
 			#address-cells = <1>;
 			#size-cells = <1>;