| Message ID | 20190124195900.22620-17-jagan@amarulasolutions.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/sun4i: Allwinner A64 MIPI-DSI support | expand |
On Fri, Jan 25, 2019 at 01:28:54AM +0530, Jagan Teki wrote: > The A64 has a MIPI-DSI block which is similar to A31. > > Add dsi, dphy nodes with A31 fallback compatible and finally > connect the dsi node to tcon0 node to make proper DSI pipeline. > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> > --- > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 47 +++++++++++++++++++ > 1 file changed, 47 insertions(+) > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > index cdc154b14a7e..e18d81aff813 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > @@ -358,6 +358,12 @@ > #address-cells = <1>; > #size-cells = <0>; > reg = <1>; > + > + tcon0_out_dsi: endpoint@1 { > + reg = <1>; > + remote-endpoint = <&dsi_in_tcon0>; > + allwinner,tcon-channel = <1>; > + }; > }; > }; > }; > @@ -935,6 +941,47 @@ > status = "disabled"; > }; > > + dsi: dsi@1ca0000 { > + compatible = "allwinner,sun50i-a64-mipi-dsi", > + "allwinner,sun6i-a31-mipi-dsi"; > + reg = <0x01ca0000 0x1000>; > + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_MIPI_DSI>, > + <&ccu CLK_DSI_DPHY>; This one looks weird. There's only a single clock in the A64, and it seems to be for the D-PHY only. And the rate is fixed at 148.5 MHz apparently, as opposed to the current code that is running at twice that speed. Maxime
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index cdc154b14a7e..e18d81aff813 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -358,6 +358,12 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; + + tcon0_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_tcon0>; + allwinner,tcon-channel = <1>; + }; }; }; }; @@ -935,6 +941,47 @@ status = "disabled"; }; + dsi: dsi@1ca0000 { + compatible = "allwinner,sun50i-a64-mipi-dsi", + "allwinner,sun6i-a31-mipi-dsi"; + reg = <0x01ca0000 0x1000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_MIPI_DSI>, + <&ccu CLK_DSI_DPHY>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_MIPI_DSI>; + phys = <&dphy>; + phy-names = "dphy"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + dsi_in_tcon0: endpoint { + remote-endpoint = <&tcon0_out_dsi>; + }; + }; + }; + }; + + dphy: d-phy@1ca1000 { + compatible = "allwinner,sun50i-a64-mipi-dphy", + "allwinner,sun6i-a31-mipi-dphy"; + reg = <0x01ca1000 0x1000>; + clocks = <&ccu CLK_BUS_MIPI_DSI>, + <&ccu CLK_DSI_DPHY>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_MIPI_DSI>; + status = "disabled"; + #phy-cells = <0>; + }; + csi: csi@1cb0000 { compatible = "allwinner,sun50i-a64-csi"; reg = <0x01cb0000 0x1000>;
The A64 has a MIPI-DSI block which is similar to A31. Add dsi, dphy nodes with A31 fallback compatible and finally connect the dsi node to tcon0 node to make proper DSI pipeline. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+)