| Message ID | 20190126212824.15641-1-festevam@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: imx8mq: Add ECSPI support | expand |
> Add support for the three ECSPI ports present on i.MX8MQ. > > Signed-off-by: Fabio Estevam <festevam@gmail.com> > --- > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 39 +++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 892063a7c26c..45b9d4a8b0da 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -26,6 +26,9 @@ > serial1 = &uart2; > serial2 = &uart3; > serial3 = &uart4; > + spi0 = &ecspi1; > + spi1 = &ecspi2; > + spi2 = &ecspi3; > }; > > ckil: clock-ckil { > @@ -381,6 +384,42 @@ > #size-cells = <1>; > ranges = <0x30800000 0x30800000 0x400000>; > > + ecspi1: spi@30820000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; > + reg = <0x0 0x30820000 0x0 0x10000>; AIPS3 in upstream tree uses #address-cells = <1> and size-cells = <1>, so 'reg' property of this and other nodes needs to be adjusted for that (vendor tree uses 2/2). With that small problem fixed: Tested-by: Andrey Smirnov <andrew.smirnov@gmail.com> Thanks, Andrey Smirnov
Hi Fabio, Am Samstag, den 26.01.2019, 19:28 -0200 schrieb Fabio Estevam: > Add support for the three ECSPI ports present on i.MX8MQ. > > Signed-off-by: Fabio Estevam <festevam@gmail.com> > --- > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 39 +++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 892063a7c26c..45b9d4a8b0da 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -26,6 +26,9 @@ > serial1 = &uart2; > serial2 = &uart3; > serial3 = &uart4; > + spi0 = &ecspi1; > + spi1 = &ecspi2; > + spi2 = &ecspi3; > }; > > ckil: clock-ckil { > @@ -381,6 +384,42 @@ > #size-cells = <1>; > ranges = <0x30800000 0x30800000 0x400000>; > > + ecspi1: spi@30820000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; > + reg = <0x0 0x30820000 0x0 0x10000>; reg is a single address and size cell in the upstream DT, as all peripherals are below the 4GB mark, so we just expand the addresses by using a DT range in the soc node. Regards, Lucas > + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, > + <&clk IMX8MQ_CLK_ECSPI1_ROOT>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + ecspi2: spi@30830000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; > + reg = <0x0 0x30830000 0x0 0x10000>; > + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, > + <&clk IMX8MQ_CLK_ECSPI2_ROOT>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > + ecspi3: spi@30840000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; > + reg = <0x0 0x30840000 0x0 0x10000>; > + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, > + <&clk IMX8MQ_CLK_ECSPI3_ROOT>; > + clock-names = "ipg", "per"; > + status = "disabled"; > + }; > + > uart1: serial@30860000 { > compatible = "fsl,imx8mq-uart", > "fsl,imx6q-uart";
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 892063a7c26c..45b9d4a8b0da 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -26,6 +26,9 @@ serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &ecspi3; }; ckil: clock-ckil { @@ -381,6 +384,42 @@ #size-cells = <1>; ranges = <0x30800000 0x30800000 0x400000>; + ecspi1: spi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; + reg = <0x0 0x30820000 0x0 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, + <&clk IMX8MQ_CLK_ECSPI1_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: spi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; + reg = <0x0 0x30830000 0x0 0x10000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, + <&clk IMX8MQ_CLK_ECSPI2_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: spi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; + reg = <0x0 0x30840000 0x0 0x10000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, + <&clk IMX8MQ_CLK_ECSPI3_ROOT>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + uart1: serial@30860000 { compatible = "fsl,imx8mq-uart", "fsl,imx6q-uart";
Add support for the three ECSPI ports present on i.MX8MQ. Signed-off-by: Fabio Estevam <festevam@gmail.com> --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 39 +++++++++++++++++++++++ 1 file changed, 39 insertions(+)