| Message ID | 0476beba-ea1f-7675-aa08-573b74e84f4e@cogentembedded.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | sh_eth: implement simple RX checksum offload | expand |
On Sun, Jan 27, 2019 at 08:38:33PM +0300, Sergei Shtylyov wrote: > The RZ/A1H (R7S721000) SoC manual describes the Ether MAC's RX checksum > offload the same way as it's implemented in the EtherAVB MACs... > > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Regarding this and the remaining patches in this series, which add rx-csum offload support in the sh_eth driver for various SoCs: has this been tested?
On 01/28/2019 03:20 PM, Simon Horman wrote: >> The RZ/A1H (R7S721000) SoC manual describes the Ether MAC's RX checksum >> offload the same way as it's implemented in the EtherAVB MACs... >> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > Regarding this and the remaining patches in this series, > which add rx-csum offload support in the sh_eth driver for > various SoCs: has this been tested? As I said, I've only tested it on R8A77980. MBR, Sergei
On Mon, Jan 28, 2019 at 06:21:11PM +0300, Sergei Shtylyov wrote: > On 01/28/2019 03:20 PM, Simon Horman wrote: > > >> The RZ/A1H (R7S721000) SoC manual describes the Ether MAC's RX checksum > >> offload the same way as it's implemented in the EtherAVB MACs... > >> > >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > > > > Regarding this and the remaining patches in this series, > > which add rx-csum offload support in the sh_eth driver for > > various SoCs: has this been tested? > > As I said, I've only tested it on R8A77980. Thanks, I missed that. As you may have guessed the implication of my question is that IMHO it would be best only to add this feature to SoCs where it has been tested.
Hello! On 01/29/2019 11:00 AM, Simon Horman wrote: >>>> The RZ/A1H (R7S721000) SoC manual describes the Ether MAC's RX checksum >>>> offload the same way as it's implemented in the EtherAVB MACs... >>>> >>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> >>> >>> Regarding this and the remaining patches in this series, >>> which add rx-csum offload support in the sh_eth driver for >>> various SoCs: has this been tested? >> >> As I said, I've only tested it on R8A77980. And still hoping Geert would be able to test on R8A7740. > > Thanks, I missed that. > > As you may have guessed the implication of my question is that > IMHO it would be best only to add this feature to SoCs where > it has been tested. You don't trust the manuals? :-) MBR, Sergei
On Tuesday, January 29, 2019, Sergei Shtylyov wrote: > On 01/29/2019 11:00 AM, Simon Horman wrote: > > As you may have guessed the implication of my question is that > > IMHO it would be best only to add this feature to SoCs where > > it has been tested. > > You don't trust the manuals? :-) > > MBR, Sergei How were you testing this feature with the R8A77980? Chris
On 01/29/2019 06:02 PM, Chris Brandt wrote: >>> As you may have guessed the implication of my question is that >>> IMHO it would be best only to add this feature to SoCs where >>> it has been tested. >> >> You don't trust the manuals? :-) >> >> MBR, Sergei > > How were you testing this feature with the R8A77980? Like Simon, I used perf/netperf, you can see it in the patch #2's description. You have other ideas? > Chris MBR, Sergei
On Tue, Jan 29, 2019 at 01:37:38PM +0300, Sergei Shtylyov wrote: > Hello! > > On 01/29/2019 11:00 AM, Simon Horman wrote: > > >>>> The RZ/A1H (R7S721000) SoC manual describes the Ether MAC's RX checksum > >>>> offload the same way as it's implemented in the EtherAVB MACs... > >>>> > >>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> > >>> > >>> Regarding this and the remaining patches in this series, > >>> which add rx-csum offload support in the sh_eth driver for > >>> various SoCs: has this been tested? > >> > >> As I said, I've only tested it on R8A77980. > > And still hoping Geert would be able to test on R8A7740. > > > > > Thanks, I missed that. > > > > As you may have guessed the implication of my question is that > > IMHO it would be best only to add this feature to SoCs where > > it has been tested. > > You don't trust the manuals? :-) As a rule I do not. But sometimes I have to anyway.
Index: net-next/drivers/net/ethernet/renesas/sh_eth.c =================================================================== --- net-next.orig/drivers/net/ethernet/renesas/sh_eth.c +++ net-next/drivers/net/ethernet/renesas/sh_eth.c @@ -620,6 +620,7 @@ static struct sh_eth_cpu_data r7s72100_d .no_ade = 1, .xdfar_rw = 1, .csmr = 1, + .rx_csum = 1, .tsu = 1, .no_tx_cntrs = 1, };
The RZ/A1H (R7S721000) SoC manual describes the Ether MAC's RX checksum offload the same way as it's implemented in the EtherAVB MACs... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> --- drivers/net/ethernet/renesas/sh_eth.c | 1 + 1 file changed, 1 insertion(+)