| Message ID | 20190131204333.31846-5-andrew.smirnov@gmail.com (mailing list archive) |
|---|---|
| State | RFC |
| Headers | show |
| Series | PCIE support for i.MX8MQ (DT changes) | expand |
Am Donnerstag, den 31.01.2019, 12:43 -0800 schrieb Andrey Smirnov: > Add nodes for two PCIe controllers found on i.MX8MQ. > > > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> > > Cc: Shawn Guo <shawnguo@kernel.org> > > Cc: Fabio Estevam <fabio.estevam@nxp.com> > > Cc: Chris Healy <cphealy@gmail.com> > > Cc: Lucas Stach <l.stach@pengutronix.de> > > Cc: Leonard Crestez <leonard.crestez@nxp.com> > > Cc: "A.s. Dong" <aisheng.dong@nxp.com> > > Cc: Richard Zhu <hongxing.zhu@nxp.com> > Cc: linux-imx@nxp.com > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > --- > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 68 +++++++++++++++++++++++ > 1 file changed, 68 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 89babc531380..d20e5c7e21a3 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -6,6 +6,7 @@ > > #include <dt-bindings/clock/imx8mq-clock.h> > #include <dt-bindings/power/imx8mq-power.h> > +#include <dt-bindings/reset/imx8mq-reset.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include "imx8mq-pinfunc.h" > @@ -539,6 +540,73 @@ > }; > > }; > > + pcie0: pcie@33800000 { > + compatible = "fsl,imx8mq-pcie"; > + reg = <0x33800000 0x400000>, > + <0x1ff00000 0x80000>; > + reg-names = "dbi", "config"; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + bus-range = <0x00 0xff>; > + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ > + 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ > + num-lanes = <1>; > + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ I don't think this IRQ is documented in any binding yet. > + interrupt-names = "msi"; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0 0 0 0x7>; > + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, > + <&clk IMX8MQ_CLK_PCIE1_AUX>, This is not the PCIe bus clock. The bus clock is whatever drives the ref clock of the external bus. So on the i.MX8M-EVK this would be the fixed clock generated by U1302. The right thing to properly describe the HW is to extend the PCIe driver to look for the aux clock on i.MX8M, just like we do with the axi_inbound_clk on i.MX6SX. Regards, Lucas > + <&clk IMX8MQ_CLK_PCIE1_PHY>; > + clock-names = "pcie", "pcie_bus", "pcie_phy"; > + fsl,max-link-speed = <2>; > + power-domains = <&pgc_pcie>; > + resets = <&src IMX8MQ_RESET_PCIEPHY>, > + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, > + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; > + reset-names = "pciephy", "apps", "turnoff"; > + status = "disabled"; > + }; >
On Thu, Feb 7, 2019 at 6:27 AM Lucas Stach <l.stach@pengutronix.de> wrote: > > Am Donnerstag, den 31.01.2019, 12:43 -0800 schrieb Andrey Smirnov: > > Add nodes for two PCIe controllers found on i.MX8MQ. > > > > > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> > > > Cc: Shawn Guo <shawnguo@kernel.org> > > > Cc: Fabio Estevam <fabio.estevam@nxp.com> > > > Cc: Chris Healy <cphealy@gmail.com> > > > Cc: Lucas Stach <l.stach@pengutronix.de> > > > Cc: Leonard Crestez <leonard.crestez@nxp.com> > > > Cc: "A.s. Dong" <aisheng.dong@nxp.com> > > > Cc: Richard Zhu <hongxing.zhu@nxp.com> > > Cc: linux-imx@nxp.com > > Cc: linux-arm-kernel@lists.infradead.org > > Cc: linux-kernel@vger.kernel.org > > --- > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 68 +++++++++++++++++++++++ > > 1 file changed, 68 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > index 89babc531380..d20e5c7e21a3 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > @@ -6,6 +6,7 @@ > > > > #include <dt-bindings/clock/imx8mq-clock.h> > > #include <dt-bindings/power/imx8mq-power.h> > > +#include <dt-bindings/reset/imx8mq-reset.h> > > #include <dt-bindings/gpio/gpio.h> > > #include <dt-bindings/interrupt-controller/arm-gic.h> > > #include "imx8mq-pinfunc.h" > > @@ -539,6 +540,73 @@ > > }; > > > > }; > > > > + pcie0: pcie@33800000 { > > + compatible = "fsl,imx8mq-pcie"; > > + reg = <0x33800000 0x400000>, > > + <0x1ff00000 0x80000>; > > + reg-names = "dbi", "config"; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + device_type = "pci"; > > + bus-range = <0x00 0xff>; > > + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ > > + 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ > > + num-lanes = <1>; > > + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ > > I don't think this IRQ is documented in any binding yet. > A leftover from vendor tree. Will drop in v2. > > + interrupt-names = "msi"; > > + #interrupt-cells = <1>; > > + interrupt-map-mask = <0 0 0 0x7>; > > + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, > > + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, > > + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, > > + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, > > + <&clk IMX8MQ_CLK_PCIE1_AUX>, > > This is not the PCIe bus clock. The bus clock is whatever drives the > ref clock of the external bus. So on the i.MX8M-EVK this would be the > fixed clock generated by U1302. > > The right thing to properly describe the HW is to extend the PCIe > driver to look for the aux clock on i.MX8M, just like we do with the > axi_inbound_clk on i.MX6SX. > OK, will update it in v2 and send a corresponding patch to PCI tree once everything is agreed upon. Thanks, Andrey Smirnov
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 89babc531380..d20e5c7e21a3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -6,6 +6,7 @@ #include <dt-bindings/clock/imx8mq-clock.h> #include <dt-bindings/power/imx8mq-power.h> +#include <dt-bindings/reset/imx8mq-reset.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include "imx8mq-pinfunc.h" @@ -539,6 +540,73 @@ }; }; + pcie0: pcie@33800000 { + compatible = "fsl,imx8mq-pcie"; + reg = <0x33800000 0x400000>, + <0x1ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x00 0xff>; + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, + <&clk IMX8MQ_CLK_PCIE1_AUX>, + <&clk IMX8MQ_CLK_PCIE1_PHY>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIEPHY>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + status = "disabled"; + }; + + pcie1: pcie@0x33c00000 { + compatible = "fsl,imx8mq-pcie"; + reg = <0x33c00000 0x400000>, + <0x27f00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */ + 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie>; + resets = <&src IMX8MQ_RESET_PCIEPHY2>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + status = "disabled"; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */
Add nodes for two PCIe controllers found on i.MX8MQ. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Lucas Stach <l.stach@pengutronix.de> Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 68 +++++++++++++++++++++++ 1 file changed, 68 insertions(+)