| Message ID | 37f573797e18fc22f8f78d0a62550b6d5e460a8d.1549875778.git.mesihkilinc@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Timer & SPI support for Allwinner suniv F1C100s | expand |
On Mon, Feb 11, 2019 at 12:21:12PM +0300, Mesih Kilinc wrote: > PC0~PC4 is pin group for SPI0. PA0~PA4 is pin group for SPI1. > Add device tree nodes for this groups. > > Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> > --- > arch/arm/boot/dts/suniv-f1c100s.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi > index 1b332d9..a92a411 100644 > --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi > +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi > @@ -96,6 +96,16 @@ > pins = "PE0", "PE1"; > function = "uart0"; > }; > + > + spi0_pc_pins: spi0-pc-pins { > + pins = "PC0", "PC1", "PC2", "PC3"; > + function = "spi0"; > + }; > + > + spi1_pa_pins: spi1-pa-pins { > + pins = "PA0", "PA1", "PA2", "PA3"; > + function = "spi1"; > + }; Are they the only options for the muxing of the SPI pins? if so, you'd need to remove the pin bank, and to set the pinctrl-0 and pinctrl-names in the DTSI. We also move the CS pin out in a separate group to accomodate devices that use a GPIO instead. Maxime
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 1b332d9..a92a411 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -96,6 +96,16 @@ pins = "PE0", "PE1"; function = "uart0"; }; + + spi0_pc_pins: spi0-pc-pins { + pins = "PC0", "PC1", "PC2", "PC3"; + function = "spi0"; + }; + + spi1_pa_pins: spi1-pa-pins { + pins = "PA0", "PA1", "PA2", "PA3"; + function = "spi1"; + }; }; timer@1c20c00 {
PC0~PC4 is pin group for SPI0. PA0~PA4 is pin group for SPI1. Add device tree nodes for this groups. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)