Message ID | 20190212175052.6310-4-krzk@kernel.org (mailing list archive) |
---|---|
State | Awaiting Upstream, archived |
Headers | show |
Series | clk/ARM: exynos: Add ADC to Exynos5410 (Odroid XU) | expand |
Hi, On 19. 2. 13. 오전 2:50, Krzysztof Kozlowski wrote: > Add the gate clock for ADC block on Exynos5410. > > Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> > --- > drivers/clk/samsung/clk-exynos5410.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c > index 0a0b09591e6f..b2da2c8fa0c7 100644 > --- a/drivers/clk/samsung/clk-exynos5410.c > +++ b/drivers/clk/samsung/clk-exynos5410.c > @@ -209,6 +209,7 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { > GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0), > GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0), > GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0), > + GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0), > GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0), > > GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0", > I checked it on Exynos5410 TRM. Looks good to me. Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c index 0a0b09591e6f..b2da2c8fa0c7 100644 --- a/drivers/clk/samsung/clk-exynos5410.c +++ b/drivers/clk/samsung/clk-exynos5410.c @@ -209,6 +209,7 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0), GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0), GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0), + GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0), GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0), GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
Add the gate clock for ADC block on Exynos5410. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> --- drivers/clk/samsung/clk-exynos5410.c | 1 + 1 file changed, 1 insertion(+)