| Message ID | 1549299218-44714-1-git-send-email-andrew.murray@arm.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | KVM: arm/arm64: add support for chained counters | expand |
On Mon, 4 Feb 2019 16:53:33 +0000 Andrew Murray <andrew.murray@arm.com> wrote: > ARMv8 provides support for chained PMU counters, where an event type > of 0x001E is set for odd-numbered counters, the event counter will > increment by one for each overflow of the preceding even-numbered > counter. Let's emulate this in KVM by creating a 64 bit perf counter > when a user chains two emulated counters together. > > Testing has been performed by hard-coding hwc->sample_period in > __hw_perf_event_init (arm_pmu.c) to a small value, this results in > regular overflows (for non sampling events). The following command > was then used to measure chained and non-chained instruction cycles: > > perf stat -e armv8_pmuv3/long=1,inst_retired/u \ > -e armv8_pmuv3/long=0,inst_retired/u dd if=/dev/zero bs=1M \ > count=10 | gzip > /dev/null > > The reported values were identical (and for non-chained was in the > same ballpark when running on a kernel without this patchset). Debug > was added to verify that the guest received overflow interrupts for > the chain counter. Hi Andrew, We're getting quite close to the merge window, and I need to wrap up the pull request pretty soon. If you want this to make it into 5.1, you'll have to respin it pretty quickly (right now, basically...), addressing the comments Suzuki and Julien raised. Thanks, M.
On Mon, Feb 18, 2019 at 08:52:17AM +0000, Marc Zyngier wrote: > On Mon, 4 Feb 2019 16:53:33 +0000 > Andrew Murray <andrew.murray@arm.com> wrote: > > > ARMv8 provides support for chained PMU counters, where an event type > > of 0x001E is set for odd-numbered counters, the event counter will > > increment by one for each overflow of the preceding even-numbered > > counter. Let's emulate this in KVM by creating a 64 bit perf counter > > when a user chains two emulated counters together. > > > > Testing has been performed by hard-coding hwc->sample_period in > > __hw_perf_event_init (arm_pmu.c) to a small value, this results in > > regular overflows (for non sampling events). The following command > > was then used to measure chained and non-chained instruction cycles: > > > > perf stat -e armv8_pmuv3/long=1,inst_retired/u \ > > -e armv8_pmuv3/long=0,inst_retired/u dd if=/dev/zero bs=1M \ > > count=10 | gzip > /dev/null > > > > The reported values were identical (and for non-chained was in the > > same ballpark when running on a kernel without this patchset). Debug > > was added to verify that the guest received overflow interrupts for > > the chain counter. > > Hi Andrew, > > We're getting quite close to the merge window, and I need to wrap up the > pull request pretty soon. If you want this to make it into 5.1, you'll > have to respin it pretty quickly (right now, basically...), addressing > the comments Suzuki and Julien raised. > Thanks for the prompt, I'll send this out very shortly. Thanks, Andrew Murray > Thanks, > > M. > -- > Without deviation from the norm, progress is not possible.
ARMv8 provides support for chained PMU counters, where an event type of 0x001E is set for odd-numbered counters, the event counter will increment by one for each overflow of the preceding even-numbered counter. Let's emulate this in KVM by creating a 64 bit perf counter when a user chains two emulated counters together. Testing has been performed by hard-coding hwc->sample_period in __hw_perf_event_init (arm_pmu.c) to a small value, this results in regular overflows (for non sampling events). The following command was then used to measure chained and non-chained instruction cycles: perf stat -e armv8_pmuv3/long=1,inst_retired/u \ -e armv8_pmuv3/long=0,inst_retired/u dd if=/dev/zero bs=1M \ count=10 | gzip > /dev/null The reported values were identical (and for non-chained was in the same ballpark when running on a kernel without this patchset). Debug was added to verify that the guest received overflow interrupts for the chain counter. Changes since v1: - Rename kvm_pmu_{enable,disable}_counter to reflect that they can operate on multiple counters at once and use these functions where possible - Fix bugs with overflow handing, kvm_pmu_get_counter_value did not take into consideration the perf counter value overflowing the low counter - Ensure PMCCFILTR_EL0 is used when operating on the cycle counter - Rename kvm_pmu_reenable_enabled_{pair, single} and similar - Always create perf event disabled to simplify logic elsewhere - Move PMCNTENSET_EL0 test to kvm_pmu_enable_counter_mask Andrew Murray (5): KVM: arm/arm64: rename kvm_pmu_{enable/disable}_counter functions KVM: arm/arm64: extract duplicated code to own function KVM: arm/arm64: re-create event when setting counter value KVM: arm/arm64: lazily create perf events on enable KVM: arm/arm64: support chained PMU counters arch/arm64/kvm/sys_regs.c | 4 +- include/kvm/arm_pmu.h | 9 +- virt/kvm/arm/pmu.c | 409 ++++++++++++++++++++++++++++++++++++++-------- 3 files changed, 352 insertions(+), 70 deletions(-)