Message ID | 20190214104047.1173-7-gabriel.fernandez@st.com (mailing list archive) |
---|---|
State | Accepted, archived |
Headers | show |
Series | update STM32MP1 clocks | expand |
Quoting gabriel.fernandez@st.com (2019-02-14 02:40:46) > From: Gabriel Fernandez <gabriel.fernandez@st.com> > > The divisor of ethptp_k and ck_hse_rtc clocks is: 'value register > plus one'. > Then CLK_DIVIDER_ALLOW_ZERO flag has no effect and is useless here. > > Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> > --- Applied to clk-next
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index 8958bc11ff05..ca987632564e 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -1959,11 +1959,10 @@ static const struct clock_config stm32mp1_clock_cfg[] = { CLK_SET_RATE_NO_REPARENT, _NO_GATE, _MMUX(M_ETHCK), - _DIV(RCC_ETHCKSELR, 4, 4, CLK_DIVIDER_ALLOW_ZERO, NULL)), + _DIV(RCC_ETHCKSELR, 4, 4, 0, NULL)), /* RTC clock */ - DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7, - CLK_DIVIDER_ALLOW_ZERO), + DIV(NO_ID, "ck_hse_rtc", "ck_hse", 0, RCC_RTCDIVR, 0, 7, 0), COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_PARENT,