| Message ID | 1551781151-5562-2-git-send-email-l.luba@partner.samsung.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | [v5,1/8] clk: samsung: add needed IDs for DMC clocks in Exynos5420 | expand |
On Tue, 5 Mar 2019 11:19:04 +0100, Lukasz Luba wrote: > Define new IDs for clocks used by Dynamic Memory Controller in > Exynos5422 SoC. > > Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> > --- > include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++- > 1 file changed, 17 insertions(+), 1 deletion(-) > Please add Acked-by/Reviewed-by tags when posting new versions. However, there's no need to repost patches *only* to add the tags. The upstream maintainer will do that for acks received on the version they apply. If a tag was not added on purpose, please state why and what changed.
Hi Rob, On 3/11/19 11:06 PM, Rob Herring wrote: > On Tue, 5 Mar 2019 11:19:04 +0100, Lukasz Luba wrote: >> Define new IDs for clocks used by Dynamic Memory Controller in >> Exynos5422 SoC. >> >> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> >> --- >> include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++- >> 1 file changed, 17 insertions(+), 1 deletion(-) >> > > Please add Acked-by/Reviewed-by tags when posting new versions. However, > there's no need to repost patches *only* to add the tags. The upstream > maintainer will do that for acks received on the version they apply. > > If a tag was not added on purpose, please state why and what changed. I have skipped your ACK because of the hack which is implemented in v5 clocks. Chanwoo refused the driver code because it uses 2 registers from the clock register set without Common Clock Framework API. He said that he will not accept this code and I have to figure out new approach using CCF. Thus, I have modeled these two registers as 'gates', but these registers are for Dynamic Memory Controller PAUSE feature (which stops transactions) and the other is for switching between two set of registers with timings for the LPDDR3 memory (normal operation and alternative clock source operation aka 'bypass'). These registers should be (in my opinion) in the DMC registers and not in the clocks. Sylwester pointed out offline that it could be done using regmap. These are the problematic clocks added in v5: +#define CLK_CDREX_PAUSE 531 +#define CLK_CDREX_TIMING_SET 532 I have mentioned about it in the cover letter, but you are right I could also add a comment for this particular patch that I have skipped your ACK. Thank you for sharing the information about the process. I will keep it in mind next time and will add a comment below the commit message for a particular patch and explicit information in cover letter that I am not including an ACK. Regards, Lukasz > >
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 355f469..abb1842 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -60,6 +60,7 @@ #define CLK_MAU_EPLL 159 #define CLK_SCLK_HSIC_12M 160 #define CLK_SCLK_MPHY_IXTAL24 161 +#define CLK_SCLK_BPLL 162 /* gate clocks */ #define CLK_UART0 257 @@ -195,6 +196,18 @@ #define CLK_ACLK432_CAM 518 #define CLK_ACLK_FL1550_CAM 519 #define CLK_ACLK550_CAM 520 +#define CLK_CLKM_PHY0 521 +#define CLK_CLKM_PHY1 522 +#define CLK_ACLK_PPMU_DREX0_0 523 +#define CLK_ACLK_PPMU_DREX0_1 524 +#define CLK_ACLK_PPMU_DREX1_0 525 +#define CLK_ACLK_PPMU_DREX1_1 526 +#define CLK_PCLK_PPMU_DREX0_0 527 +#define CLK_PCLK_PPMU_DREX0_1 528 +#define CLK_PCLK_PPMU_DREX1_0 529 +#define CLK_PCLK_PPMU_DREX1_1 530 +#define CLK_CDREX_PAUSE 531 +#define CLK_CDREX_TIMING_SET 532 /* mux clocks */ #define CLK_MOUT_HDMI 640 @@ -217,6 +230,8 @@ #define CLK_MOUT_EPLL 657 #define CLK_MOUT_MAU_EPLL 658 #define CLK_MOUT_USER_MAU_EPLL 659 +#define CLK_MOUT_SCLK_SPLL 660 +#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661 /* divider clocks */ #define CLK_DOUT_PIXEL 768 @@ -248,8 +263,9 @@ #define CLK_DOUT_CCLK_DREX0 794 #define CLK_DOUT_CLK2X_PHY0 795 #define CLK_DOUT_PCLK_CORE_MEM 796 +#define CLK_FF_DOUT_SPLL2 797 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 797 +#define CLK_NR_CLKS 798 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
Define new IDs for clocks used by Dynamic Memory Controller in Exynos5422 SoC. Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> --- include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-)