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[PULL] target/riscv: Convert to decodetree

Message ID 20190312131526.14710-1-palmer@sifive.com (mailing list archive)
State New, archived
Headers show
Series [PULL] target/riscv: Convert to decodetree | expand

Pull-request

git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-sf3

Message

Palmer Dabbelt March 12, 2019, 1:14 p.m. UTC 
The following changes since commit 377b155bde451d5ac545fbdcdfbf6ca17a4228f5:

  Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2019-03-11 18:26:37 +0000)

are available in the Git repository at:

  git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-sf3

for you to fetch changes up to a971f8ae0e8ab6fab1eee199961b1ea2f4d876f7:

  target/riscv: Remove decode_RV32_64G() (2019-03-12 03:08:34 -0700)

----------------------------------------------------------------
target/riscv: Convert to decodetree

Bastian: this patchset converts the RISC-V decoder to decodetree in four major steps:

1) Convert 32-bit instructions to decodetree [Patch 1-15]:
    Many of the gen_* functions are called by the decode functions for 16-bit
    and 32-bit functions. If we move translation code from the gen_*
    functions to the generated trans_* functions of decode-tree, we get a lot of
    duplication. Therefore, we mostly generate calls to the old gen_* function
    which are properly replaced after step 2).

    Each of the trans_ functions are grouped into files corresponding to their
    ISA extension, e.g. addi which is in RV32I is translated in the file
    'trans_rvi.inc.c'.

2) Convert 16-bit instructions to decodetree [Patch 16-18]:
    All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
    we convert the arguments in the 16 bit trans_ function to the arguments of
    the corresponding 32 bit instruction and call the 32 bit trans_ function.

3) Remove old manual decoding in gen_* function [Patch 19-29]:
    this move all manual translation code into the trans_* instructions of
    decode tree, such that we can remove the old decode_* functions.

Palmer: This, with some additional cleanup patches, passed Alistar's
testing on rv32 and rv64 as well as my testing on rv64, so I think it's
good to go.  I've run my standard test against this exact tag.  I
haven't tested the OSX build because I didn't find an OSX machine (I'm
traveling), but I removed the offending commits so hopefully we're safe.

----------------------------------------------------------------
Bastian Koppelmann (29):
      target/riscv: Activate decodetree and implemnt LUI & AUIPC
      target/riscv: Convert RVXI branch insns to decodetree
      target/riscv: Convert RV32I load/store insns to decodetree
      target/riscv: Convert RV64I load/store insns to decodetree
      target/riscv: Convert RVXI arithmetic insns to decodetree
      target/riscv: Convert RVXI fence insns to decodetree
      target/riscv: Convert RVXI csr insns to decodetree
      target/riscv: Convert RVXM insns to decodetree
      target/riscv: Convert RV32A insns to decodetree
      target/riscv: Convert RV64A insns to decodetree
      target/riscv: Convert RV32F insns to decodetree
      target/riscv: Convert RV64F insns to decodetree
      target/riscv: Convert RV32D insns to decodetree
      target/riscv: Convert RV64D insns to decodetree
      target/riscv: Convert RV priv insns to decodetree
      target/riscv: Convert quadrant 0 of RVXC insns to decodetree
      target/riscv: Convert quadrant 1 of RVXC insns to decodetree
      target/riscv: Convert quadrant 2 of RVXC insns to decodetree
      target/riscv: Remove gen_jalr()
      target/riscv: Remove manual decoding from gen_branch()
      target/riscv: Remove manual decoding from gen_load()
      target/riscv: Remove manual decoding from gen_store()
      target/riscv: Move gen_arith_imm() decoding into trans_* functions
      target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
      target/riscv: Remove shift and slt insn manual decoding
      target/riscv: Remove manual decoding of RV32/64M insn
      target/riscv: Rename trans_arith to gen_arith
      target/riscv: Remove gen_system()
      target/riscv: Remove decode_RV32_64G()

 target/riscv/Makefile.objs                     |   19 +
 target/riscv/insn16.decode                     |  129 ++
 target/riscv/insn32-64.decode                  |   72 +
 target/riscv/insn32.decode                     |  201 +++
 target/riscv/insn_trans/trans_privileged.inc.c |  110 ++
 target/riscv/insn_trans/trans_rva.inc.c        |  218 +++
 target/riscv/insn_trans/trans_rvc.inc.c        |  327 +++++
 target/riscv/insn_trans/trans_rvd.inc.c        |  442 ++++++
 target/riscv/insn_trans/trans_rvf.inc.c        |  439 ++++++
 target/riscv/insn_trans/trans_rvi.inc.c        |  568 ++++++++
 target/riscv/insn_trans/trans_rvm.inc.c        |  120 ++
 target/riscv/translate.c                       | 1847 ++++--------------------
 12 files changed, 2897 insertions(+), 1595 deletions(-)
 create mode 100644 target/riscv/insn16.decode
 create mode 100644 target/riscv/insn32-64.decode
 create mode 100644 target/riscv/insn32.decode
 create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c

Comments

Peter Maydell March 12, 2019, 6:31 p.m. UTC | #1 
On Tue, 12 Mar 2019 at 13:15, Palmer Dabbelt <palmer@sifive.com> wrote:
>
> The following changes since commit 377b155bde451d5ac545fbdcdfbf6ca17a4228f5:
>
>   Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2019-03-11 18:26:37 +0000)
>
> are available in the Git repository at:
>
>   git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-sf3
>
> for you to fetch changes up to a971f8ae0e8ab6fab1eee199961b1ea2f4d876f7:
>
>   target/riscv: Remove decode_RV32_64G() (2019-03-12 03:08:34 -0700)
>
> ----------------------------------------------------------------
> target/riscv: Convert to decodetree


I'm still seeing some errors about redefining typedefs, I'm afraid:

target/riscv/decode_insn16.inc.c:102:28: error: redefinition of
typedef 'arg_c_addi16sp_lui' is a C11 feature
[-Werror,-Wtypedef-redefinition]
target/riscv/decode_insn16.inc.c:122:17: error: redefinition of
typedef 'arg_c_j' is a C11 feature [-Werror,-Wtypedef-redefinition]
target/riscv/decode_insn16.inc.c:134:26: error: redefinition of
typedef 'arg_c_flwsp_ldsp' is a C11 feature
[-Werror,-Wtypedef-redefinition]
target/riscv/decode_insn16.inc.c:144:26: error: redefinition of
typedef 'arg_c_fswsp_sdsp' is a C11 feature
[-Werror,-Wtypedef-redefinition]
target/riscv/decode_insn16.inc.c:102:28: error: redefinition of
typedef 'arg_c_addi16sp_lui' is a C11 feature
[-Werror,-Wtypedef-redefinition]
target/riscv/decode_insn16.inc.c:122:17: error: redefinition of
typedef 'arg_c_j' is a C11 feature [-Werror,-Wtypedef-redefinition]
target/riscv/decode_insn16.inc.c:134:26: error: redefinition of
typedef 'arg_c_flwsp_ldsp' is a C11 feature
[-Werror,-Wtypedef-redefinition]
target/riscv/decode_insn16.inc.c:144:26: error: redefinition of
typedef 'arg_c_fswsp_sdsp' is a C11 feature
[-Werror,-Wtypedef-redefinition]

thanks
-- PMM
Bastian Koppelmann March 13, 2019, 9:31 a.m. UTC | #2 
On 3/12/19 7:31 PM, Peter Maydell wrote:
> On Tue, 12 Mar 2019 at 13:15, Palmer Dabbelt <palmer@sifive.com> wrote:
>> The following changes since commit 377b155bde451d5ac545fbdcdfbf6ca17a4228f5:
>>
>>    Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging (2019-03-11 18:26:37 +0000)
>>
>> are available in the Git repository at:
>>
>>    git://github.com/palmer-dabbelt/qemu.git tags/riscv-for-master-4.0-sf3
>>
>> for you to fetch changes up to a971f8ae0e8ab6fab1eee199961b1ea2f4d876f7:
>>
>>    target/riscv: Remove decode_RV32_64G() (2019-03-12 03:08:34 -0700)
>>
>> ----------------------------------------------------------------
>> target/riscv: Convert to decodetree
>
> I'm still seeing some errors about redefining typedefs, I'm afraid:
>
> target/riscv/decode_insn16.inc.c:102:28: error: redefinition of
> typedef 'arg_c_addi16sp_lui' is a C11 feature
> [-Werror,-Wtypedef-redefinition]
> target/riscv/decode_insn16.inc.c:122:17: error: redefinition of
> typedef 'arg_c_j' is a C11 feature [-Werror,-Wtypedef-redefinition]
> target/riscv/decode_insn16.inc.c:134:26: error: redefinition of
> typedef 'arg_c_flwsp_ldsp' is a C11 feature
> [-Werror,-Wtypedef-redefinition]
> target/riscv/decode_insn16.inc.c:144:26: error: redefinition of
> typedef 'arg_c_fswsp_sdsp' is a C11 feature
> [-Werror,-Wtypedef-redefinition]
> target/riscv/decode_insn16.inc.c:102:28: error: redefinition of
> typedef 'arg_c_addi16sp_lui' is a C11 feature
> [-Werror,-Wtypedef-redefinition]
> target/riscv/decode_insn16.inc.c:122:17: error: redefinition of
> typedef 'arg_c_j' is a C11 feature [-Werror,-Wtypedef-redefinition]
> target/riscv/decode_insn16.inc.c:134:26: error: redefinition of
> typedef 'arg_c_flwsp_ldsp' is a C11 feature
> [-Werror,-Wtypedef-redefinition]
> target/riscv/decode_insn16.inc.c:144:26: error: redefinition of
> typedef 'arg_c_fswsp_sdsp' is a C11 feature
> [-Werror,-Wtypedef-redefinition]
>
> thanks
> -- PMM
>

Hi Peter,

this should fix it:

diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode
index 0829e3bc59..1a461616aa 100644
--- a/target/riscv/insn16.decode
+++ b/target/riscv/insn16.decode
@@ -50,15 +50,15 @@
  &cs_dw     uimm   rs1 rs2
  &cb        imm    rs1
  &cr               rd  rs2
-&c_j       imm
+&cj       imm
  &c_shift   shamt      rd

  &c_ld      uimm  rd
  &c_sd      uimm  rs2

-&c_addi16sp_lui  imm_lui imm_addi16sp rd
-&c_flwsp_ldsp    uimm_flwsp uimm_ldsp rd
-&c_fswsp_sdsp    uimm_fswsp uimm_sdsp rs2
+&caddi16sp_lui  imm_lui imm_addi16sp rd
+&cflwsp_ldsp    uimm_flwsp uimm_ldsp rd
+&cfswsp_sdsp    uimm_fswsp uimm_sdsp rs2

  # Formats 16:
  @cr        ....  ..... .....  .. &cr rs2=%rs2_5  %rd
@@ -72,17 +72,17 @@
  @cs_d      ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_d rs1=%rs1_3  
rs2=%rs2_3
  @cs_w      ... ... ... .. ... .. &cs_dw  uimm=%uimm_cl_w rs1=%rs1_3  
rs2=%rs2_3
  @cb        ... ... ... .. ... .. &cb     imm=%imm_cb rs1=%rs1_3
-@cj        ...    ........... .. &c_j    imm=%imm_cj
+@cj        ...    ........... .. &cj    imm=%imm_cj

  @c_ld      ... . .....  ..... .. &c_ld uimm=%uimm_6bit_ld  %rd
  @c_lw      ... . .....  ..... .. &c_ld uimm=%uimm_6bit_lw  %rd
  @c_sd      ... . .....  ..... .. &c_sd uimm=%uimm_6bit_sd  rs2=%rs2_5
  @c_sw      ... . .....  ..... .. &c_sd uimm=%uimm_6bit_sw  rs2=%rs2_5

-@c_addi16sp_lui ... .  ..... ..... .. &c_addi16sp_lui %imm_lui 
%imm_addi16sp %rd
-@c_flwsp_ldsp   ... .  ..... ..... .. &c_flwsp_ldsp 
uimm_flwsp=%uimm_6bit_lw \
+@c_addi16sp_lui ... .  ..... ..... .. &caddi16sp_lui %imm_lui 
%imm_addi16sp %rd
+@c_flwsp_ldsp   ... .  ..... ..... .. &cflwsp_ldsp 
uimm_flwsp=%uimm_6bit_lw \
      uimm_ldsp=%uimm_6bit_ld %rd
-@c_fswsp_sdsp   ... .  ..... ..... .. &c_fswsp_sdsp 
uimm_fswsp=%uimm_6bit_sw \
+@c_fswsp_sdsp   ... .  ..... ..... .. &cfswsp_sdsp 
uimm_fswsp=%uimm_6bit_sw \
      uimm_sdsp=%uimm_6bit_sd rs2=%rs2_5

  @c_shift        ... . .. ... ..... .. &c_shift rd=%rs1_3 
shamt=%nzuimm_6bit


@Palmer: I send a fixed version of the offending patch.

Cheers,

Bastian