| Message ID | 20190307151342.7381-6-narmstrong@baylibre.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: g12a: Add peripherals | expand |
Hi Neil and Jerome, On Thu, Mar 7, 2019 at 4:14 PM Neil Armstrong <narmstrong@baylibre.com> wrote: > > From: Jerome Brunet <jbrunet@baylibre.com> > > Add the reset controller device of g12a SoC family > > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > index f8f055c49f9a..2a700bb45d04 100644 > --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > @@ -245,6 +245,13 @@ > #size-cells = <2>; > ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; > > + reset: reset-controller@1004 { > + compatible = "amlogic,meson-g12a-reset", > + "amlogic,meson-axg-reset"; > + reg = <0x0 0x1004 0x0 0x9c>; > + #reset-cells = <1>; > + }; I tried to compare this with what is publicly available in buildroot_openlinux_kernel_4.9_fbdev_20180706 - unfortunately this is harder than I thought: the buildroot kernel doesn't define the reset controller in mesong12a.dtsi so I tried to follow the code in the HDMITX driver instead: kernel/aml-4.9/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_txlx.c uses P_RESET0_REGISTER and P_RESET2_REGISTER these are defined in kernel/aml-4.9/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/txlx_reg.h using: > #define RESET_CBUS_REG_IDX 5 > #define BASE_REG_OFFSET 24 > #define RESET_CBUS_REG_ADDR(reg) \ > ((RESET_CBUS_REG_IDX << BASE_REG_OFFSET) + (reg << 2)) > > #define RESET0_REGISTER 0x01 > #define P_RESET0_REGISTER RESET_CBUS_REG_ADDR(RESET0_REGISTER) when I do the maths: (5 << 24) + (0x01 << 2) = 0x5000004 The GX SoCs have the reset controller at cbus + 0x4404 however, the offset may have changed in G12A because the SAR ADC offset also changed (just one example). Do you have any hint how to verify the CBUS offset (0x1004) of the reset controller? Regards Martin
Le 15/03/2019 22:31, Martin Blumenstingl a écrit : > Hi Neil and Jerome, > > On Thu, Mar 7, 2019 at 4:14 PM Neil Armstrong <narmstrong@baylibre.com> wrote: >> >> From: Jerome Brunet <jbrunet@baylibre.com> >> >> Add the reset controller device of g12a SoC family >> >> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> >> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> >> --- >> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi >> index f8f055c49f9a..2a700bb45d04 100644 >> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi >> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi >> @@ -245,6 +245,13 @@ >> #size-cells = <2>; >> ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; >> >> + reset: reset-controller@1004 { >> + compatible = "amlogic,meson-g12a-reset", >> + "amlogic,meson-axg-reset"; >> + reg = <0x0 0x1004 0x0 0x9c>; >> + #reset-cells = <1>; >> + }; > I tried to compare this with what is publicly available in > buildroot_openlinux_kernel_4.9_fbdev_20180706 - unfortunately this is > harder than I thought: > the buildroot kernel doesn't define the reset controller in mesong12a.dtsi > > so I tried to follow the code in the HDMITX driver instead: > kernel/aml-4.9/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hw_txlx.c > uses P_RESET0_REGISTER and P_RESET2_REGISTER > these are defined in > kernel/aml-4.9/drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/txlx_reg.h > using: >> #define RESET_CBUS_REG_IDX 5 >> #define BASE_REG_OFFSET 24 >> #define RESET_CBUS_REG_ADDR(reg) \ >> ((RESET_CBUS_REG_IDX << BASE_REG_OFFSET) + (reg << 2)) >> >> #define RESET0_REGISTER 0x01 >> #define P_RESET0_REGISTER RESET_CBUS_REG_ADDR(RESET0_REGISTER) > > when I do the maths: > (5 << 24) + (0x01 << 2) = 0x5000004 > > The GX SoCs have the reset controller at cbus + 0x4404 > however, the offset may have changed in G12A because the SAR ADC > offset also changed (just one example). > > Do you have any hint how to verify the CBUS offset (0x1004) of the > reset controller? You can find base the address found in the G12A DT for the usb2 phy : https://github.com/hardkernel/linux/blob/odroidn2-4.9.y/arch/arm64/boot/dts/amlogic/mesong12a.dtsi#L379 Neil > > > Regards > Martin >
Hi Neil, On Sat, Mar 16, 2019 at 3:32 PM Neil Armstrong <narmstrong@baylibre.com> wrote: [...] > > Do you have any hint how to verify the CBUS offset (0x1004) of the > > reset controller? > > You can find base the address found in the G12A DT for the usb2 phy : > https://github.com/hardkernel/linux/blob/odroidn2-4.9.y/arch/arm64/boot/dts/amlogic/mesong12a.dtsi#L379 perfect, thank you! feel free to add my: Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Regards Martin
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi index f8f055c49f9a..2a700bb45d04 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi @@ -245,6 +245,13 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; + reset: reset-controller@1004 { + compatible = "amlogic,meson-g12a-reset", + "amlogic,meson-axg-reset"; + reg = <0x0 0x1004 0x0 0x9c>; + #reset-cells = <1>; + }; + clk_msr: clock-measure@18000 { compatible = "amlogic,meson-g12a-clk-measure"; reg = <0x0 0x18000 0x0 0x10>;