diff mbox series

[8/9] arm64: dts: meson: g12a: Add G12A USB nodes

Message ID 20190307151342.7381-9-narmstrong@baylibre.com (mailing list archive)
State New, archived
Headers show
Series arm64: dts: g12a: Add peripherals | expand

Commit Message

Neil Armstrong March 7, 2019, 3:13 p.m. UTC
This patch adds the nodes for the USB Complex found in the Amlogic
G12A SoC.

It includes the :
- 2 USB2 PHYs
- 1 USB3 + PCIE Combo PHY
- the USB Glue with it's DWC2 and DWC3 sub-nodes

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
 arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 78 +++++++++++++++++++++
 1 file changed, 78 insertions(+)

Comments

Martin Blumenstingl March 15, 2019, 9:40 p.m. UTC | #1
On Thu, Mar 7, 2019 at 4:15 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> This patch adds the nodes for the USB Complex found in the Amlogic
> G12A SoC.
>
> It includes the :
> - 2 USB2 PHYs
> - 1 USB3 + PCIE Combo PHY
> - the USB Glue with it's DWC2 and DWC3 sub-nodes
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

[...]
> +                               g-tx-fifo-size = <128 128 16 16 16>;
I'm not sure about these values but it seems you have already successfully them.
buildroot_openlinux_kernel_4.9_fbdev_20180706 uses the following
values (which are identical to the ones on GXL/GXM, but using the
values below I couldn't get dwc2 to work on GXL when I tried it last):
  dev_tx_fifo_size[0] = 128;
  dev_tx_fifo_size[1] = 128;
  dev_tx_fifo_size[2] = 128;
  dev_tx_fifo_size[3] = 16;
  dev_tx_fifo_size[4] = 16;

Thus I'm still giving my Reviewed-by based on the assumption that the
g-tx-fifo-size values you have are working (at least for you)


Regards
Martin
Neil Armstrong March 16, 2019, 2:37 p.m. UTC | #2
Le 15/03/2019 22:40, Martin Blumenstingl a écrit :
> On Thu, Mar 7, 2019 at 4:15 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> This patch adds the nodes for the USB Complex found in the Amlogic
>> G12A SoC.
>>
>> It includes the :
>> - 2 USB2 PHYs
>> - 1 USB3 + PCIE Combo PHY
>> - the USB Glue with it's DWC2 and DWC3 sub-nodes
>>
>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> 
> [...]
>> +                               g-tx-fifo-size = <128 128 16 16 16>;
> I'm not sure about these values but it seems you have already successfully them.
> buildroot_openlinux_kernel_4.9_fbdev_20180706 uses the following
> values (which are identical to the ones on GXL/GXM, but using the
> values below I couldn't get dwc2 to work on GXL when I tried it last):
>   dev_tx_fifo_size[0] = 128;
>   dev_tx_fifo_size[1] = 128;
>   dev_tx_fifo_size[2] = 128;
>   dev_tx_fifo_size[3] = 16;
>   dev_tx_fifo_size[4] = 16;


Same for me, only <128 128 16 16 16> worked for me.

> 
> Thus I'm still giving my Reviewed-by based on the assumption that the
> g-tx-fifo-size values you have are working (at least for you)

Indeed, I tried the amlogic values without success, I suspect the driver they use
(the Sysnopsys out-of-tree driver) uses these values differently.

Thanks,
Neil

> 
> 
> Regards
> Martin
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
index 3bcddd412aa1..991883ea023c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
@@ -3,9 +3,13 @@ 
  * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
  */
 
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/g12a-clkc.h>
+#include <dt-bindings/clock/g12a-aoclkc.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/amlogic,meson-g12a-reset.h>
 
 / {
 	compatible = "amlogic,g12a";
@@ -170,6 +174,26 @@ 
 				};
 			};
 
+			usb2_phy0: phy@36000 {
+				compatible = "amlogic,g12a-usb2-phy";
+				reg = <0x0 0x36000 0x0 0x2000>;
+				clocks = <&xtal>;
+				clock-names = "xtal";
+				resets = <&reset RESET_USB_PHY20>;
+				reset-names = "phy";
+				#phy-cells = <0>;
+			};
+
+			usb2_phy1: phy@3a000 {
+				compatible = "amlogic,g12a-usb2-phy";
+				reg = <0x0 0x3a000 0x0 0x2000>;
+				clocks = <&xtal>;
+				clock-names = "xtal";
+				resets = <&reset RESET_USB_PHY21>;
+				reset-names = "phy";
+				#phy-cells = <0>;
+			};
+
 			hiu: bus@3c000 {
 				compatible = "simple-bus";
 				reg = <0x0 0x3c000 0x0 0x1400>;
@@ -190,6 +214,18 @@ 
 					};
 				};
 			};
+
+			usb3_pcie_phy: phy@46000 {
+				compatible = "amlogic,g12a-usb3-pcie-phy";
+				reg = <0x0 0x46000 0x0 0x2000>;
+				clocks = <&clkc CLKID_PCIE_PLL>;
+				clock-names = "ref_clk";
+				resets = <&reset RESET_PCIE_PHY>;
+				reset-names = "phy";
+				assigned-clocks = <&clkc CLKID_PCIE_PLL>;
+				assigned-clock-rates = <100000000>;
+				#phy-cells = <1>;
+			};
 		};
 
 		aobus: bus@ff800000 {
@@ -353,6 +389,48 @@ 
 				status = "disabled";
 			};
 		};
+
+		usb: usb@ffe09000 {
+			status = "disabled";
+			compatible = "amlogic,meson-g12a-usb-ctrl";
+			reg = <0x0 0xffe09000 0x0 0xa0>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			clocks = <&clkc CLKID_USB>;
+			resets = <&reset RESET_USB>;
+
+			dr_mode = "otg";
+
+			phys = <&usb2_phy0>, <&usb2_phy1>,
+			       <&usb3_pcie_phy PHY_TYPE_USB3>;
+			phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0";
+
+			dwc2: usb@ff400000 {
+				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
+				reg = <0x0 0xff400000 0x0 0x40000>;
+				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
+				clock-names = "ddr";
+				phys = <&usb2_phy1>;
+				dr_mode = "peripheral";
+				g-rx-fifo-size = <192>;
+				g-np-tx-fifo-size = <128>;
+				g-tx-fifo-size = <128 128 16 16 16>;
+				status = "disabled";
+			};
+
+			dwc3: usb@ff500000 {
+				compatible = "snps,dwc3";
+				reg = <0x0 0xff500000 0x0 0x100000>;
+				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+				dr_mode = "host";
+				snps,dis_u2_susphy_quirk;
+				snps,quirk-frame-length-adjustment;
+			};
+		};
 	};
 
 	timer {