| Message ID | 20190313211844.29416-7-ilina@codeaurora.org (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | support wakeup capable GPIOs | expand |
On Wed, Mar 13, 2019 at 03:18:40PM -0600, Lina Iyer wrote: > SDM845 SoC has an always-on interrupt controller (PDC) with select GPIO > routed to the PDC as interrupts that can be used to wake the system up > from deep low power modes and suspend. > > Cc: devicetree@vger.kernel.org > Signed-off-by: Lina Iyer <ilina@codeaurora.org> > --- > .../devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) I still don't love this being specific to wake-up, but don't have a better suggestion. One nit, otherwise: Reviewed-by: Rob Herring <robh@kernel.org> > > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt > index 665aadb5ea28..f0fedbc5d41a 100644 > --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt > +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt > @@ -29,6 +29,11 @@ SDM845 platform. > Definition: must be 2. Specifying the pin number and flags, as defined > in <dt-bindings/interrupt-controller/irq.h> > > +- wakeup-parent: > + Usage: optional > + Value type: <phandle> > + Definition: A phandle to the wakeup interrupt controller for the SoC. > + > - gpio-controller: > Usage: required > Value type: <none> > @@ -53,7 +58,6 @@ pin, a group, or a list of pins or groups. This configuration can include the > mux function to select on those pin(s)/group(s), and various pin configuration > parameters, such as pull-up, drive strength, etc. > > - > PIN CONFIGURATION NODES: > > The name of each subnode is not important; all subnodes should be enumerated > @@ -160,6 +164,7 @@ Example: > #gpio-cells = <2>; > interrupt-controller; > #interrupt-cells = <2>; > + wake-parent = <&pdc_intc>; wakeup-parent > > qup9_active: qup9-active { > mux { > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >
Thanks for the review Rob. On Fri, Mar 15 2019 at 17:37 -0600, Rob Herring wrote: >On Wed, Mar 13, 2019 at 03:18:40PM -0600, Lina Iyer wrote: >> SDM845 SoC has an always-on interrupt controller (PDC) with select GPIO >> routed to the PDC as interrupts that can be used to wake the system up >> from deep low power modes and suspend. >> >> Cc: devicetree@vger.kernel.org >> Signed-off-by: Lina Iyer <ilina@codeaurora.org> >> --- >> .../devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt | 7 ++++++- >> 1 file changed, 6 insertions(+), 1 deletion(-) > >I still don't love this being specific to wake-up, but don't have a >better suggestion. One nit, otherwise: > I added this to interrupts.txt. I will remove this, if the documentation in [PATCH v4 03/10] of/irq: document properties for wakeup interrupt parent of this series works. -- Lina >Reviewed-by: Rob Herring <robh@kernel.org> > >> >> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt >> index 665aadb5ea28..f0fedbc5d41a 100644 >> --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt >> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt >> @@ -29,6 +29,11 @@ SDM845 platform. >> Definition: must be 2. Specifying the pin number and flags, as defined >> in <dt-bindings/interrupt-controller/irq.h> >> >> +- wakeup-parent: >> + Usage: optional >> + Value type: <phandle> >> + Definition: A phandle to the wakeup interrupt controller for the SoC. >> + >> - gpio-controller: >> Usage: required >> Value type: <none> >> @@ -53,7 +58,6 @@ pin, a group, or a list of pins or groups. This configuration can include the >> mux function to select on those pin(s)/group(s), and various pin configuration >> parameters, such as pull-up, drive strength, etc. >> >> - >> PIN CONFIGURATION NODES: >> >> The name of each subnode is not important; all subnodes should be enumerated >> @@ -160,6 +164,7 @@ Example: >> #gpio-cells = <2>; >> interrupt-controller; >> #interrupt-cells = <2>; >> + wake-parent = <&pdc_intc>; > >wakeup-parent > >> >> qup9_active: qup9-active { >> mux { >> -- >> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, >> a Linux Foundation Collaborative Project >>
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt index 665aadb5ea28..f0fedbc5d41a 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt @@ -29,6 +29,11 @@ SDM845 platform. Definition: must be 2. Specifying the pin number and flags, as defined in <dt-bindings/interrupt-controller/irq.h> +- wakeup-parent: + Usage: optional + Value type: <phandle> + Definition: A phandle to the wakeup interrupt controller for the SoC. + - gpio-controller: Usage: required Value type: <none> @@ -53,7 +58,6 @@ pin, a group, or a list of pins or groups. This configuration can include the mux function to select on those pin(s)/group(s), and various pin configuration parameters, such as pull-up, drive strength, etc. - PIN CONFIGURATION NODES: The name of each subnode is not important; all subnodes should be enumerated @@ -160,6 +164,7 @@ Example: #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + wake-parent = <&pdc_intc>; qup9_active: qup9-active { mux {
SDM845 SoC has an always-on interrupt controller (PDC) with select GPIO routed to the PDC as interrupts that can be used to wake the system up from deep low power modes and suspend. Cc: devicetree@vger.kernel.org Signed-off-by: Lina Iyer <ilina@codeaurora.org> --- .../devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-)