| Message ID | 1553350688-39627-1-git-send-email-like.xu@linux.intel.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Intel Virtual PMU Optimization | expand |
On Sat, Mar 23, 2019 at 10:18:03PM +0800, Like Xu wrote: > === Brief description === > > This proposal for Intel vPMU is still committed to optimize the basic > functionality by reducing the PMU virtualization overhead and not a blind > pass-through of the PMU. The proposal applies to existing models, in short, > is "host perf would hand over control to kvm after counter allocation". > > The pmc_reprogram_counter is a heavyweight and high frequency operation > which goes through the host perf software stack to create a perf event for > counter assignment, this could take millions of nanoseconds. The current > vPMU always does reprogram_counter when the guest changes the eventsel, > fixctrl, and global_ctrl msrs. This brings too much overhead to the usage > of perf inside the guest, especially the guest PMI handling and context > switching of guest threads with perf in use. I think I asked for starting with making pmc_reprogram_counter() less retarded. I'm not seeing that here. > We optimize the current vPMU to work in this manner: > > (1) rely on the existing host perf (perf_event_create_kernel_counter) > to allocate counters for in-use vPMC and always try to reuse events; > (2) vPMU captures guest accesses to the eventsel and fixctrl msr directly > to the hardware msr that the corresponding host event is scheduled on > and avoid pollution from host is also needed in its partial runtime; If you do pass-through; how do you deal with event constraints? > (3) save and restore the counter state during vCPU scheduling in hooks; > (4) apply a lazy approach to release the vPMC's perf event. That is, if > the vPMC isn't used in a fixed sched slice, its event will be released. > > In the use of vPMC, the vPMU always focus on the assigned resources and > guest perf would significantly benefit from direct access to hardware and > may not care about runtime state of perf_event created by host and always > try not to pay for their maintenance. However to avoid events entering into > any unexpected state, calling pmc_read_counter in appropriate is necessary. what?! I can't follow that, and the quick look I had at the patches doesn't seem to help. I did note it is intel only and that is really sad. It also makes a mess of who programs what msr when.
> > We optimize the current vPMU to work in this manner: > > > > (1) rely on the existing host perf (perf_event_create_kernel_counter) > > to allocate counters for in-use vPMC and always try to reuse events; > > (2) vPMU captures guest accesses to the eventsel and fixctrl msr directly > > to the hardware msr that the corresponding host event is scheduled on > > and avoid pollution from host is also needed in its partial runtime; > > If you do pass-through; how do you deal with event constraints? The guest has to deal with them. It already needs to know the model number to program the right events, can as well know the constraints too. For architectural events that don't need the model number it's not a problem because they don't have constraints. -Andi
On 2019/3/24 7:15, Andi Kleen wrote: >>> We optimize the current vPMU to work in this manner: >>> >>> (1) rely on the existing host perf (perf_event_create_kernel_counter) >>> to allocate counters for in-use vPMC and always try to reuse events; >>> (2) vPMU captures guest accesses to the eventsel and fixctrl msr directly >>> to the hardware msr that the corresponding host event is scheduled on >>> and avoid pollution from host is also needed in its partial runtime; >> >> If you do pass-through; how do you deal with event constraints? > > The guest has to deal with them. It already needs to know > the model number to program the right events, can as well know > the constraints too. > > For architectural events that don't need the model number it's > not a problem because they don't have constraints. > > -Andi > I agree this version doesn't seem to keep an eye on host perf event constraints deliberately: 1. Based on my limited knowledge, assuming the model number means hwc->idx. 2. The guest event constraints would be constructed into hwc->config_base value which is pmc->eventsel and pmu->fixed_ctr_ctrl from KVM point of view. 3. The guest PMU has same semantic model on virt hardware limitation as the host does with real PMU (related CPUID/PERF_MSR expose this part of information to guest). 3. Guest perf scheduler would make sure the guest event constraints could dance with right guest model number. 4. vPMU would make sure the guest vPMC get the right guest model number by hard-code EVENT_PINNED or just fail with creation. 5. This patch directly apply the guest hwc->config_base value to host assigned hardware without consent from host perf(a bit deceptive but practical for reducing the number of reprogram calls). === OR ==== If we insist on passing guest event constraints to host perf, this proposal may need the following changes: Because the guest configuration of hwc->config_base mostly only toggles the enable bit of eventsel or fixctrl,it is not necessary to do reprogram_counter because it's serving the same guest perf event. The event creation is only needed when guest writes a complete new value to eventsel or fixctrl.Codes for guest MSR_P6_EVNTSEL0 trap for example may be modified to be like this: u64 diff = pmc->eventsel ^ data; if (intel_pmc_is_assigned(pmc) && diff != ARCH_PERFMON_EVENTSEL_ENABLE) { intel_pmu_save_guest_pmc(pmu, pmc->idx); intel_pmc_stop_counter(pmc); } reprogram_gp_counter(pmc, data); Does this seem to satisfy our needs? It makes everything easier to correct me if I'm wrong.
On 2019/3/24 1:28, Peter Zijlstra wrote: > On Sat, Mar 23, 2019 at 10:18:03PM +0800, Like Xu wrote: >> === Brief description === >> >> This proposal for Intel vPMU is still committed to optimize the basic >> functionality by reducing the PMU virtualization overhead and not a blind >> pass-through of the PMU. The proposal applies to existing models, in short, >> is "host perf would hand over control to kvm after counter allocation". >> >> The pmc_reprogram_counter is a heavyweight and high frequency operation >> which goes through the host perf software stack to create a perf event for >> counter assignment, this could take millions of nanoseconds. The current >> vPMU always does reprogram_counter when the guest changes the eventsel, >> fixctrl, and global_ctrl msrs. This brings too much overhead to the usage >> of perf inside the guest, especially the guest PMI handling and context >> switching of guest threads with perf in use. > > I think I asked for starting with making pmc_reprogram_counter() less > retarded. I'm not seeing that here. Do you mean pass perf_event_attr to refactor pmc_reprogram_counter via paravirt ? Please share more details. > >> We optimize the current vPMU to work in this manner: >> >> (1) rely on the existing host perf (perf_event_create_kernel_counter) >> to allocate counters for in-use vPMC and always try to reuse events; >> (2) vPMU captures guest accesses to the eventsel and fixctrl msr directly >> to the hardware msr that the corresponding host event is scheduled on >> and avoid pollution from host is also needed in its partial runtime; > > If you do pass-through; how do you deal with event constraints > >> (3) save and restore the counter state during vCPU scheduling in hooks; >> (4) apply a lazy approach to release the vPMC's perf event. That is, if >> the vPMC isn't used in a fixed sched slice, its event will be released. >> >> In the use of vPMC, the vPMU always focus on the assigned resources and >> guest perf would significantly benefit from direct access to hardware and >> may not care about runtime state of perf_event created by host and always >> try not to pay for their maintenance. However to avoid events entering into >> any unexpected state, calling pmc_read_counter in appropriate is necessary. > > what?! The patch will reuse the created events as much as possible for same guest vPMC which may has different config_base in its partial runtime. The pmc_read_counter is designed to be called in kvm_pmu_rdpmc and pmc_stop_counter as legacy does and it's not for vPMU functionality but for host perf maintenance (seems to be gone in code,Oops). > > I can't follow that, and the quick look I had at the patches doesn't > seem to help. I did note it is intel only and that is really sad. The basic idea of optimization is x86 generic, and the implementation is not intentional cause I could not access non-Intel machines and verified it. > > It also makes a mess of who programs what msr when. > who programs: vPMU does as usual in pmc_reprogram_counter what msr: host perf scheduler make decisions and I'm not sure the hosy perf would do cross-mapping scheduling which means to assign a host fixed counter to guest gp counter and vice versa. when programs: every time to call reprogram_gp/fixed_counter && pmc_is_assigned(pmc) is false; check the fifth pacth for details.
On Mon, Mar 25, 2019 at 02:47:32PM +0800, Like Xu wrote: > On 2019/3/24 1:28, Peter Zijlstra wrote: > > On Sat, Mar 23, 2019 at 10:18:03PM +0800, Like Xu wrote: > > > === Brief description === > > > > > > This proposal for Intel vPMU is still committed to optimize the basic > > > functionality by reducing the PMU virtualization overhead and not a blind > > > pass-through of the PMU. The proposal applies to existing models, in short, > > > is "host perf would hand over control to kvm after counter allocation". > > > > > > The pmc_reprogram_counter is a heavyweight and high frequency operation > > > which goes through the host perf software stack to create a perf event for > > > counter assignment, this could take millions of nanoseconds. The current > > > vPMU always does reprogram_counter when the guest changes the eventsel, > > > fixctrl, and global_ctrl msrs. This brings too much overhead to the usage > > > of perf inside the guest, especially the guest PMI handling and context > > > switching of guest threads with perf in use. > > > > I think I asked for starting with making pmc_reprogram_counter() less > > retarded. I'm not seeing that here. > > Do you mean pass perf_event_attr to refactor pmc_reprogram_counter > via paravirt ? Please share more details. I mean nothing; I'm trying to understand wth you're doing. > > > We optimize the current vPMU to work in this manner: > > > > > > (1) rely on the existing host perf (perf_event_create_kernel_counter) > > > to allocate counters for in-use vPMC and always try to reuse events; > > > (2) vPMU captures guest accesses to the eventsel and fixctrl msr directly > > > to the hardware msr that the corresponding host event is scheduled on > > > and avoid pollution from host is also needed in its partial runtime; > > > > If you do pass-through; how do you deal with event constraints > > > > (3) save and restore the counter state during vCPU scheduling in hooks; > > > (4) apply a lazy approach to release the vPMC's perf event. That is, if > > > the vPMC isn't used in a fixed sched slice, its event will be released. > > > > > > In the use of vPMC, the vPMU always focus on the assigned resources and > > > guest perf would significantly benefit from direct access to hardware and > > > may not care about runtime state of perf_event created by host and always > > > try not to pay for their maintenance. However to avoid events entering into > > > any unexpected state, calling pmc_read_counter in appropriate is necessary. > > > > what?! > > The patch will reuse the created events as much as possible for same guest > vPMC which may has different config_base in its partial runtime. again. what?! > The pmc_read_counter is designed to be called in kvm_pmu_rdpmc and > pmc_stop_counter as legacy does and it's not for vPMU functionality but for > host perf maintenance (seems to be gone in code,Oops). > > > > > I can't follow that, and the quick look I had at the patches doesn't > > seem to help. I did note it is intel only and that is really sad. > > The basic idea of optimization is x86 generic, and the implementation is not > intentional cause I could not access non-Intel machines and verified it. > > > > > It also makes a mess of who programs what msr when. > > > > who programs: vPMU does as usual in pmc_reprogram_counter > > what msr: host perf scheduler make decisions and I'm not sure the hosy perf > would do cross-mapping scheduling which means to assign a host fixed counter > to guest gp counter and vice versa. > > when programs: every time to call reprogram_gp/fixed_counter && > pmc_is_assigned(pmc) is false; check the fifth pacth for details. I'm not going to reverse engineer this; if you can't write coherent descriptions, this isn't going anywhere. It isn't going anywhere anyway, its insane. You let perf do all its normal things and then discard the results by avoiding the wrmsr. Then you fudge a second wrmsr path somewhere. Please, just make the existing event dtrt.
> It isn't going anywhere anyway, its insane. You let perf do all its > normal things and then discard the results by avoiding the wrmsr. > > Then you fudge a second wrmsr path somewhere. > > Please, just make the existing event dtrt. I still think the right way is to force an event to a counter from an internal field. And then set that field from KVM. This is quite straight forward to do in the event scheduler. I did it for some experimential PEBS virtualization patches which require the same because they have to expose the counter indexes inside the PEBS record to the guest. -Andi
On 03/25/2019 03:19 PM, Peter Zijlstra wrote: > On Mon, Mar 25, 2019 at 02:47:32PM +0800, Like Xu wrote: >> On 2019/3/24 1:28, Peter Zijlstra wrote: >>> On Sat, Mar 23, 2019 at 10:18:03PM +0800, Like Xu wrote: >>>> === Brief description === >>>> >>>> This proposal for Intel vPMU is still committed to optimize the basic >>>> functionality by reducing the PMU virtualization overhead and not a blind >>>> pass-through of the PMU. The proposal applies to existing models, in short, >>>> is "host perf would hand over control to kvm after counter allocation". >>>> >>>> The pmc_reprogram_counter is a heavyweight and high frequency operation >>>> which goes through the host perf software stack to create a perf event for >>>> counter assignment, this could take millions of nanoseconds. The current >>>> vPMU always does reprogram_counter when the guest changes the eventsel, >>>> fixctrl, and global_ctrl msrs. This brings too much overhead to the usage >>>> of perf inside the guest, especially the guest PMI handling and context >>>> switching of guest threads with perf in use. >>> I think I asked for starting with making pmc_reprogram_counter() less >>> retarded. I'm not seeing that here. >> Do you mean pass perf_event_attr to refactor pmc_reprogram_counter >> via paravirt ? Please share more details. > I mean nothing; I'm trying to understand wth you're doing. I also feel the description looks confusing (sorry for being late to join in due to leaves). Also the code needs to be improved a lot. Please see the basic idea here: reprogram_counter is a heavyweight operation which goes through the perf software stack to create a perf event, this could take millions of nanoseconds. The current KVM vPMU always does reprogram_counter when the guest changes the eventsel, fixctrl, and global_ctrl msrs. This brings too much overhead to the usage of perf inside the guest, especially the guest PMI handling and context switching of guest threads with perf in use. In fact, during the guest perf event life cycle, it mostly only toggles the enable bit of eventsel or fixctrl. From the KVM point of view, if the guest only toggles the enable bits, it is not necessary to do reprogram_counter, because it is serving the same guest perf event. So the "enable bit" can be directly applied to the hardware msr that the corresponding host event is occupying. We optimize the current vPMU to work in this manner: 1) rely on the existing host perf (perf_event_create_kernel_counter) to create a perf event for each vPMC. This creation is only needed when guest writes a complete new value to eventsel or fixctrl. 2) vPMU captures guest accesses to the eventsel and fixctrl msrs. If the guest only toggles the enable bit, then we don't need to reprogram_pmc_counter, as the vPMC is serving the same guest event. So KVM only updates the enable bit directly to the hardware msr that the corresponding host event is scheduled on. 3) When the host perf reschedules perf counters and happens to have the vPMC's perf event scheduled out, KVM will do reprogram_counter. 4) We use a lazy approach to release the vPMC's perf event. That is, if the vPMC wasn't used for a vCPU time slice, the corresponding perf event will be released via kvm calling perf_event_release_kernel. Regarding who updates the underlying hardware counter: The change here is when a perf event is used by the guest (i.e. exclude_host=true or using a new flag if necessary), perf doesn't update the hardware counter (e.g. a counter's event_base and config_base), instead, the hypervisor helps to update them. Hope the above has made it clear to understand. Thanks! Best, Wei
As a toolbox treasure to developers, the Performance Monitoring Unit is designed to monitor micro architectural events which helps in analyzing how an application or operating systems are performing on the processors. Today in KVM, version 2 Architectural PMU on Intel and AMD hosts is implemented and works. With the joint efforts of the community, it would be an inspiring journey to enable all available PMU features for guest users as complete/smooth/accurate as possible. === Brief description === This proposal for Intel vPMU is still committed to optimize the basic functionality by reducing the PMU virtualization overhead and not a blind pass-through of the PMU. The proposal applies to existing models, in short, is "host perf would hand over control to kvm after counter allocation". The pmc_reprogram_counter is a heavyweight and high frequency operation which goes through the host perf software stack to create a perf event for counter assignment, this could take millions of nanoseconds. The current vPMU always does reprogram_counter when the guest changes the eventsel, fixctrl, and global_ctrl msrs. This brings too much overhead to the usage of perf inside the guest, especially the guest PMI handling and context switching of guest threads with perf in use. We optimize the current vPMU to work in this manner: (1) rely on the existing host perf (perf_event_create_kernel_counter) to allocate counters for in-use vPMC and always try to reuse events; (2) vPMU captures guest accesses to the eventsel and fixctrl msr directly to the hardware msr that the corresponding host event is scheduled on and avoid pollution from host is also needed in its partial runtime; (3) save and restore the counter state during vCPU scheduling in hooks; (4) apply a lazy approach to release the vPMC's perf event. That is, if the vPMC isn't used in a fixed sched slice, its event will be released. In the use of vPMC, the vPMU always focus on the assigned resources and guest perf would significantly benefit from direct access to hardware and may not care about runtime state of perf_event created by host and always try not to pay for their maintenance. However to avoid events entering into any unexpected state, calling pmc_read_counter in appropriate is necessary. === vPMU Overhead Comparison === For the guest perf usage like "perf stat -e branches,cpu-cycles,\ L1-icache-load-misses,branch-load-misses,branch-loads,\ dTLB-load-misses ./ftest", here are some performance numbers which show the improvement with this optimization (in nanoseconds) [1]: (1) Basic operatios latency on legacy Intel vPMU kvm_pmu_rdpmc 200 pmc_stop_counter: gp 30,000 pmc_stop_counter: fixed 2,000,000 perf_event_create_kernel_counter: gp 30,000,000 <== (mark as 3.1) perf_event_create_kernel_counter: fixed 25,000 (2) Comparison of max guest behavior latency legacy v2 enable global_ctrl 57,000,000 17,000,000 <== (3.2) disable global_ctrl 2,000,000 21,000 r/w fixed_ctrl 21,000 1,100 r/w eventsel 36,000 17,000 rdpmcl 35,000 18,000 x86_pmu.handle_irq 3,500,000 8,800 <== (3.3) (3) For 3.2, the v2 value is just a maximum value for reprogram and would be quickly weakened to neglect by reusing perf_events. In general, we can say this optimization is ~400 times (3.3) faster than the original for Intel vPMU due to a large number reduction of calls to perf_event_create_kernel_counter (3.1). (4) Comparison of guest behavior call time legacy v2 enable global_ctrl 74,000 3,000 <== (6.1) rd/wr fixed_ctrl 11,000 1,400 rd/wr eventsel 7,000,000 7,600 rdpmcl 130,000 10,000 x86_pmu.handle_irq 11 14 (5) Comparison of perf-attached thread guest context_switch latency legacy v2 context_switch, sched_in 350,000,000 4,000,000 context_switch, sched_out 55,000,000 200,000 (6) From 6.1 and table 5, We can see a substantial reduction in the runtime of a perf attached guest thread and the vPMU is no longer stuck. === vPMU Precision Comparison === We don't want to lose any precision after optimization and for perf usage like "perf record -e cpu-cycles --all-user ./ftest"here is the comparison of the profiling results with and without this optimization [1]: (1) Test in Guest without optimization: [ perf record: Woken up 2 times to write data ] [ perf record: Captured and wrote 0.437 MB perf.data (5198 samples) ] 36.95% ftest ftest [.] qux 15.68% ftest ftest [.] foo 15.45% ftest ftest [.] bar 12.32% ftest ftest [.] main 9.56% ftest libc-2.27.so [.] __random 8.87% ftest libc-2.27.so [.] __random_r 1.17% ftest ftest [.] random@plt 0.00% ftest ld-2.27.so [.] _start (2) Test in Guest with this optimization: [ perf record: Woken up 4 times to write data ] [ perf record: Captured and wrote 0.861 MB perf.data (22550 samples) ] 36.64% ftest ftest [.] qux 14.35% ftest ftest [.] foo 14.07% ftest ftest [.] bar 12.60% ftest ftest [.] main 11.73% ftest libc-2.27.so [.] __random 9.18% ftest libc-2.27.so [.] __random_r 1.42% ftest ftest [.] random@plt 0.00% ftest ld-2.27.so [.] do_lookup_x 0.00% ftest ld-2.27.so [.] _dl_new_object 0.00% ftest ld-2.27.so [.] _dl_sysdep_start 0.00% ftest ld-2.27.so [.] _start (3) Test in Host: [ perf record: Woken up 4 times to write data ] [ perf record: Captured and wrote 0.789 MB perf.data (20652 samples) ] 37.87% ftest ftest [.] qux 15.78% ftest ftest [.] foo 13.18% ftest ftest [.] main 12.14% ftest ftest [.] bar 9.85% ftest libc-2.17.so [.] __random_r 9.59% ftest libc-2.17.so [.] __random 1.59% ftest ftest [.] random@plt 0.00% ftest ld-2.17.so [.] _dl_cache_libcmp 0.00% ftest ld-2.17.so [.] _dl_start 0.00% ftest ld-2.17.so [.] _start === NEXT === This proposal is trying to respected necessary functionality from the host perf driver and bypasses the host perf subsystem software stack in most execution paths with no loss of precision compared to the legacy one. If this proposal is acceptable, here are something we could do for next: (1) If host perf wants to perceive all the events for scheduling, some event hooks could be implemented to update host perf_event with the proper counts/runtimes/state. (2) Loose the scheduling restrictions on pinned, but still keeps eyes on special specific requests (3) This series currently covers the basic perf counter virtualization. Other features, such as pebs, bts, lbr will come after this series. May be there is something wrong in the whole series and please help me reach the other side of the performance improvement with your comments. [1] Tested on Linux 5.0.0 on Intel(R) Xeon(R) CPU E5-2699 v4 @ 2.20GHz, and added "nowatchdog" to host booting parameter. The values comes from sched_clock() using tsc as guest clocksource. === Changelog === v1: Wei Wang (8): https://lkml.org/lkml/2018/11/1/937 perf/x86: add support to mask counters from host perf/x86/intel: add pmi callback support KVM/x86/vPMU: optimize intel vPMU KVM/x86/vPMU: support msr switch on vmx transitions KVM/x86/vPMU: intel_pmu_read_pmc KVM/x86/vPMU: remove some unused functions KVM/x86/vPMU: save/restore guest perf counters on vCPU switching KVM/x86/vPMU: return the counters to host if guest is torn down v2: Like Xu (5): perf/x86: avoid host changing counter state for kvm_intel events holder KVM/x86/vPMU: add pmc operations for vmx and count to track release KVM/x86/vPMU: add Intel vPMC enable/disable and save/restore support KVM/x86/vPMU: add vCPU scheduling support for hw-assigned vPMC KVM/x86/vPMU: not do reprogram_counter for Intel hw-assigned vPMC arch/x86/events/core.c | 37 ++++- arch/x86/events/intel/core.c | 5 +- arch/x86/events/perf_event.h | 13 +- arch/x86/include/asm/kvm_host.h | 2 + arch/x86/kvm/pmu.c | 34 +++++ arch/x86/kvm/pmu.h | 22 +++ arch/x86/kvm/vmx/pmu_intel.c | 329 +++++++++++++++++++++++++++++++++++++--- arch/x86/kvm/x86.c | 6 + 8 files changed, 421 insertions(+), 27 deletions(-)