| Message ID | 1553261968-5766-1-git-send-email-iuliana.prodan@nxp.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Herbert Xu |
| Headers | show |
| Series | crypto: caam - limit AXI pipeline to a depth of 1 | expand |
On 3/22/2019 3:39 PM, Iuliana Prodan wrote: > Some i.MX6 devices (imx6D, imx6Q, imx6DL, imx6S, imx6DP and imx6DQ) have > an issue wherein AXI bus transactions may not occur in the correct order. > This isn't a problem running single descriptors, but can be if running > multiple concurrent descriptors. Reworking the CAAM driver to throttle > to single requests is impractical, so this patch limits the AXI pipeline > to a depth of one (from a default of 4) to preclude this situation from > occurring. > This patch applies to known affected platforms. > > Signed-off-by: Radu Solea <radu.solea@nxp.com> > Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com> Reviewed-by: Horia Geantă <horia.geanta@nxp.com> Thanks, Horia
On Fri, Mar 22, 2019 at 03:39:28PM +0200, Iuliana Prodan wrote: > Some i.MX6 devices (imx6D, imx6Q, imx6DL, imx6S, imx6DP and imx6DQ) have > an issue wherein AXI bus transactions may not occur in the correct order. > This isn't a problem running single descriptors, but can be if running > multiple concurrent descriptors. Reworking the CAAM driver to throttle > to single requests is impractical, so this patch limits the AXI pipeline > to a depth of one (from a default of 4) to preclude this situation from > occurring. > This patch applies to known affected platforms. > > Signed-off-by: Radu Solea <radu.solea@nxp.com> > Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com> > --- > drivers/crypto/caam/ctrl.c | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) Patch applied. Thanks. Email: Herbert Xu <herbert@gondor.apana.org.au> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c index 858bdc9..e2ba3d2 100644 --- a/drivers/crypto/caam/ctrl.c +++ b/drivers/crypto/caam/ctrl.c @@ -468,6 +468,24 @@ static int caam_get_era(struct caam_ctrl __iomem *ctrl) return caam_get_era_from_hw(ctrl); } +/* + * ERRATA: imx6 devices (imx6D, imx6Q, imx6DL, imx6S, imx6DP and imx6DQ) + * have an issue wherein AXI bus transactions may not occur in the correct + * order. This isn't a problem running single descriptors, but can be if + * running multiple concurrent descriptors. Reworking the driver to throttle + * to single requests is impractical, thus the workaround is to limit the AXI + * pipeline to a depth of 1 (from it's default of 4) to preclude this situation + * from occurring. + */ +static void handle_imx6_err005766(u32 *mcr) +{ + if (of_machine_is_compatible("fsl,imx6q") || + of_machine_is_compatible("fsl,imx6dl") || + of_machine_is_compatible("fsl,imx6qp")) + clrsetbits_32(mcr, MCFGR_AXIPIPE_MASK, + 1 << MCFGR_AXIPIPE_SHIFT); +} + static const struct of_device_id caam_match[] = { { .compatible = "fsl,sec-v4.0", @@ -640,6 +658,8 @@ static int caam_probe(struct platform_device *pdev) (sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0)); + handle_imx6_err005766(&ctrl->mcr); + /* * Read the Compile Time paramters and SCFGR to determine * if Virtualization is enabled for this platform