| Message ID | 20190327151348.27402-1-narmstrong@baylibre.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Delegated to: | Neil Armstrong |
| Headers | show |
| Series | clk: meson: vid-pll-div: remove warning and return 0 on invalid config | expand |
On Wed, 2019-03-27 at 16:13 +0100, Neil Armstrong wrote: > The vid_pll_div is a programmable fractional divider, but vendor gives a > limited of known configuration value and it's corresponding fraction. > > Thus when at reset value (0) or unknown value, we cannot determine the > result rate. > > The initial behaviour was to print a warning, but the warning triggers > at each boot and when the clock tree is refreshed. > > This patch moves the print to debug and returns 0 instead of the > parent rate. > > Fixes: 72dbb8c94d0d ("clk: meson: Add vid_pll divider driver") > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > drivers/clk/meson/vid-pll-div.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
On 29/03/2019 09:39, Jerome Brunet wrote: > On Wed, 2019-03-27 at 16:13 +0100, Neil Armstrong wrote: >> The vid_pll_div is a programmable fractional divider, but vendor gives a >> limited of known configuration value and it's corresponding fraction. >> >> Thus when at reset value (0) or unknown value, we cannot determine the >> result rate. >> >> The initial behaviour was to print a warning, but the warning triggers >> at each boot and when the clock tree is refreshed. >> >> This patch moves the print to debug and returns 0 instead of the >> parent rate. >> >> Fixes: 72dbb8c94d0d ("clk: meson: Add vid_pll divider driver") >> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> >> --- >> drivers/clk/meson/vid-pll-div.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) > > Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> > Thanks, Applied to fixes/drivers Neil
diff --git a/drivers/clk/meson/vid-pll-div.c b/drivers/clk/meson/vid-pll-div.c index 08bcc01c0923..daff235bc763 100644 --- a/drivers/clk/meson/vid-pll-div.c +++ b/drivers/clk/meson/vid-pll-div.c @@ -82,8 +82,8 @@ static unsigned long meson_vid_pll_div_recalc_rate(struct clk_hw *hw, div = _get_table_val(meson_parm_read(clk->map, &pll_div->val), meson_parm_read(clk->map, &pll_div->sel)); if (!div || !div->divider) { - pr_info("%s: Invalid config value for vid_pll_div\n", __func__); - return parent_rate; + pr_debug("%s: Invalid config value for vid_pll_div\n", __func__); + return 0; } return DIV_ROUND_UP_ULL(parent_rate * div->multiplier, div->divider);
The vid_pll_div is a programmable fractional divider, but vendor gives a limited of known configuration value and it's corresponding fraction. Thus when at reset value (0) or unknown value, we cannot determine the result rate. The initial behaviour was to print a warning, but the warning triggers at each boot and when the clock tree is refreshed. This patch moves the print to debug and returns 0 instead of the parent rate. Fixes: 72dbb8c94d0d ("clk: meson: Add vid_pll divider driver") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- drivers/clk/meson/vid-pll-div.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)