| Message ID | 1553666207-11414-19-git-send-email-skomatineni@nvidia.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [V1,01/26] spi: tegra114: fix PIO transfer | expand |
On Tue, Mar 26, 2019 at 10:56:40PM -0700, Sowjanya Komatineni wrote: > This patch adds below cs timing properties to allow SPI master configuring > setup, hold and time interval between two SPI transactions to meet specific > SPI client device requirements. > CS setup time > CS hold time > CS inactive delay > DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; > t=1553666253; bh=TbJVgRAIkjok3TkKNkfcvYc4WGyZhOpiH6sUZvadGrQ=; > h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: > In-Reply-To:References:X-NVConfidentiality:MIME-Version: > Content-Type; > b=Tud9guY5XCzkjKA2k2n0+xO/vTfMTNhH1e0viAyYmlgoG/j+uSBAAmOeZucVUlmEa > rwqxlSm+rkYMUfgSWqmJXqEjgRIAqMhA32FOJmhgpblGwYUR22hnbdhbk4TcqMNsIO Something got corrupted? > +spi-client device controller properties: > +- nvidia,cs-setup-clk-count: CS setup timing parameter. > +- nvidia,cs-hold-clk-count: CS hold timing parameter. > +- nvidia,cs-inactive-cycles: CS inactive delay in terms of clock between > + transfers. Why are these being done as nVidia specific properties rather than generic ones and why are these being configured in DT rather than by the client driver? If the devices have particular timing requirements for chip select presumably that's going to apply no matter what controller or system they're used with so it seems best to configure this in the client driver and have an API that any controller can implement.
> On Tue, Mar 26, 2019 at 10:56:40PM -0700, Sowjanya Komatineni wrote: > > This patch adds below cs timing properties to allow SPI master > > configuring setup, hold and time interval between two SPI transactions > > to meet specific SPI client device requirements. > > CS setup time > > CS hold time > > CS inactive delay > > DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; > > t=1553666253; bh=TbJVgRAIkjok3TkKNkfcvYc4WGyZhOpiH6sUZvadGrQ=; > > h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: > > In-Reply-To:References:X-NVConfidentiality:MIME-Version: > > Content-Type; > > b=Tud9guY5XCzkjKA2k2n0+xO/vTfMTNhH1e0viAyYmlgoG/j+uSBAAmOeZucVUlmEa > > rwqxlSm+rkYMUfgSWqmJXqEjgRIAqMhA32FOJmhgpblGwYUR22hnbdhbk4TcqMNsIO > > Something got corrupted? Possible. Will re-send anyway with your feedback fixes. > > +spi-client device controller properties: > > +- nvidia,cs-setup-clk-count: CS setup timing parameter. > > +- nvidia,cs-hold-clk-count: CS hold timing parameter. > > +- nvidia,cs-inactive-cycles: CS inactive delay in terms of clock > > +between > > + transfers. > > Why are these being done as nVidia specific properties rather than generic ones and why are these being configured in DT rather than by the client driver? If the devices have particular timing requirements for chip select presumably that's going to apply no matter what controller or system they're used with so it seems best to configure this in the client driver and have an API that any controller can implement. These are implemented thru DT as Tegra SPI is master and master controls the timing. Some SPI slaves have specific requirements of certain CS setup/hold time and inactive cycles which SPI master should meet when driving during transfer and Tegra SPI controller supports tuning these parameters.
On Mon, Apr 01, 2019 at 05:59:57PM +0000, Sowjanya Komatineni wrote: Please fix your mail client to word wrap within paragraphs at something substantially less than 80 columns. Doing this makes your messages much easier to read and reply to. > > > +spi-client device controller properties: > > > +- nvidia,cs-setup-clk-count: CS setup timing parameter. > > > +- nvidia,cs-hold-clk-count: CS hold timing parameter. > > > +- nvidia,cs-inactive-cycles: CS inactive delay in terms of clock > > > +between > > > + transfers. > > Why are these being done as nVidia specific properties rather than > > generic ones and why are these being configured in DT rather than by > > the client driver? If the devices have particular timing > > requirements for chip select presumably that's going to apply no > > matter what controller or system they're used with so it seems best > > to configure this in the client driver and have an API that any > > controller can implement. > These are implemented thru DT as Tegra SPI is master and master controls the timing. > Some SPI slaves have specific requirements of certain CS setup/hold time and inactive cycles which SPI master should meet when driving during transfer and Tegra SPI controller supports tuning these parameters. This doesn't address the issue at all, obviously the timings for the SPI bus are going to be impelemented by the controller but that's not the issue.
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt index 9ba7c5a273b4..6167c5234b64 100644 --- a/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt @@ -23,6 +23,13 @@ Required properties: Recommended properties: - spi-max-frequency: Definition as per Documentation/devicetree/bindings/spi/spi-bus.txt + +spi-client device controller properties: +- nvidia,cs-setup-clk-count: CS setup timing parameter. +- nvidia,cs-hold-clk-count: CS hold timing parameter. +- nvidia,cs-inactive-cycles: CS inactive delay in terms of clock between + transfers. + Example: spi@7000d600 {
This patch adds below cs timing properties to allow SPI master configuring setup, hold and time interval between two SPI transactions to meet specific SPI client device requirements. CS setup time CS hold time CS inactive delay DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666253; bh=TbJVgRAIkjok3TkKNkfcvYc4WGyZhOpiH6sUZvadGrQ=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=Tud9guY5XCzkjKA2k2n0+xO/vTfMTNhH1e0viAyYmlgoG/j+uSBAAmOeZucVUlmEa rwqxlSm+rkYMUfgSWqmJXqEjgRIAqMhA32FOJmhgpblGwYUR22hnbdhbk4TcqMNsIO mXBgiIq3sOB7dKCDIv4+YSUreRrnXrvrDN0NE9zN7D+AQWYLF5dI4v+UDalNYJU2hz TusNrURxuHgtpModvYVQRPgPDv+nJ2QE6L7yZH/M6XP7jYprtQHWnHAiMwqqSXBcrf 8vlhV96anQSaGkioOUTp8ThlHSwBKLRFHRofVlrhT53K0xvTCvVst4aHvA1aq3QPw0 sVr25yohIPq7w== Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- Documentation/devicetree/bindings/spi/nvidia,tegra114-spi.txt | 7 +++++++ 1 file changed, 7 insertions(+)