| Message ID | 20190321095927.7058-9-kishon@ti.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Commit | fd8a44bd5b76dc77133f814dd63d414d49dc74c0 |
| Headers | show |
| Series | PCI: DWC/Keystone: MSI configuration cleanup | expand |
On Thu, Mar 21, 2019 at 03:29:27PM +0530, Kishon Vijay Abraham I wrote: > Platforms which populate msi_host_init, has it's own MSI controller > logic. Writing to MSI control registers on platforms which doesn't use > Designware's MSI controller logic might have side effects. To > be safe, do not write to MSI control registers if the platform uses > it's own MSI controller logic instead of Designware's MSI controller > logic. > > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > .../pci/controller/dwc/pcie-designware-host.c | 24 ++++++++++--------- > 1 file changed, 13 insertions(+), 11 deletions(-) This patch is needed regardless of the rest of the series, correct ? A.k.a. it is fixing an issue already in the mainline. Just to make sure we are not _introducing_ a bisection issue with this series up to this patch, in which case I will squash this patch into one of the previous ones, please let me know. Thanks, Lorenzo > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 498422397609..7e0ff7d428a9 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -626,17 +626,19 @@ void dw_pcie_setup_rc(struct pcie_port *pp) > > dw_pcie_setup(pci); > > - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; > - > - /* Initialize IRQ Status array */ > - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { > - pp->irq_mask[ctrl] = ~0; > - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + > - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), > - 4, pp->irq_mask[ctrl]); > - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + > - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), > - 4, ~0); > + if (!pp->ops->msi_host_init) { > + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; > + > + /* Initialize IRQ Status array */ > + for (ctrl = 0; ctrl < num_ctrls; ctrl++) { > + pp->irq_mask[ctrl] = ~0; > + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + > + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), > + 4, pp->irq_mask[ctrl]); > + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + > + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), > + 4, ~0); > + } > } > > /* Setup RC BARs */ > -- > 2.17.1 >
Hi Lorenzo, On 03/04/19 10:49 PM, Lorenzo Pieralisi wrote: > On Thu, Mar 21, 2019 at 03:29:27PM +0530, Kishon Vijay Abraham I wrote: >> Platforms which populate msi_host_init, has it's own MSI controller >> logic. Writing to MSI control registers on platforms which doesn't use >> Designware's MSI controller logic might have side effects. To >> be safe, do not write to MSI control registers if the platform uses >> it's own MSI controller logic instead of Designware's MSI controller >> logic. >> >> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> >> --- >> .../pci/controller/dwc/pcie-designware-host.c | 24 ++++++++++--------- >> 1 file changed, 13 insertions(+), 11 deletions(-) > > This patch is needed regardless of the rest of the series, correct ? > A.k.a. it is fixing an issue already in the mainline. That's correct. Thanks Kishon
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 498422397609..7e0ff7d428a9 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -626,17 +626,19 @@ void dw_pcie_setup_rc(struct pcie_port *pp) dw_pcie_setup(pci); - num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; - - /* Initialize IRQ Status array */ - for (ctrl = 0; ctrl < num_ctrls; ctrl++) { - pp->irq_mask[ctrl] = ~0; - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - 4, pp->irq_mask[ctrl]); - dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + - (ctrl * MSI_REG_CTRL_BLOCK_SIZE), - 4, ~0); + if (!pp->ops->msi_host_init) { + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + + /* Initialize IRQ Status array */ + for (ctrl = 0; ctrl < num_ctrls; ctrl++) { + pp->irq_mask[ctrl] = ~0; + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + 4, pp->irq_mask[ctrl]); + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), + 4, ~0); + } } /* Setup RC BARs */
Platforms which populate msi_host_init, has it's own MSI controller logic. Writing to MSI control registers on platforms which doesn't use Designware's MSI controller logic might have side effects. To be safe, do not write to MSI control registers if the platform uses it's own MSI controller logic instead of Designware's MSI controller logic. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- .../pci/controller/dwc/pcie-designware-host.c | 24 ++++++++++--------- 1 file changed, 13 insertions(+), 11 deletions(-)