| Message ID | 20190405234514.6183-7-megous@megous.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Delegated to: | Johannes Berg |
| Headers | show |
| Series | Add support for Orange Pi 3 | expand |
Hello! On 06.04.2019 2:45, megous@megous.com wrote: > From: Icenowy Zheng <icenowy@aosc.io> > > The PHY selection bit also exists on SoCs without an internal PHY; if > it's set to 1 (internal PHY) then the MAC will not make use of any PHY. > > This problem appears when adapting for H6, which has no real internal > PHY (the "internal PHY" on H6 is not on-die, but on a co-packaged AC200 > chip, via RMII interface at GPIO bank A), but the PHY selection bit is > set. > > Force the PHY selection bit to 0 when no external PHY to select this > problem. "Select this problem" sound weird... > Signed-off-by: Icenowy Zheng <icenowy@aosc.io> > --- > drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c > index e3e3dc44b33b..bd340e77b2ea 100644 > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c > @@ -908,6 +908,11 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) > * address. No need to mask it again. > */ > reg |= 1 << H3_EPHY_ADDR_SHIFT; > + } else { > + /* For SoCs without internal PHY the PHY selection bit should be > + * set to 0 (external PHY). > + */ > + reg &= ~(H3_EPHY_SELECT); No () should be needed here, add () around the macro body if still needed. [...] MBR, Sergei
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c index e3e3dc44b33b..bd340e77b2ea 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c @@ -908,6 +908,11 @@ static int sun8i_dwmac_set_syscon(struct stmmac_priv *priv) * address. No need to mask it again. */ reg |= 1 << H3_EPHY_ADDR_SHIFT; + } else { + /* For SoCs without internal PHY the PHY selection bit should be + * set to 0 (external PHY). + */ + reg &= ~(H3_EPHY_SELECT); } if (!of_property_read_u32(node, "allwinner,tx-delay-ps", &val)) {