diff mbox series

[PATCH/RFC] arm64: dts: renesas: ebisu, draak: Limit EtherAVB to 100Mbps

Message ID 20190408083148.23134-1-horms+renesas@verge.net.au (mailing list archive)
State Changes Requested
Delegated to: Simon Horman
Headers show
Series [PATCH/RFC] arm64: dts: renesas: ebisu, draak: Limit EtherAVB to 100Mbps | expand

Commit Message

Simon Horman April 8, 2019, 8:31 a.m. UTC 
* According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of
  August 24, 2018, the TX clock internal delay mode isn't supported
  on R-Car E3 (r8a77990) and D3 (r8a77995).

* TX clock internal delay mode is required for reliable 1Gbps communication
  using the KSZ9031RNX phy present on the Ebisu and Draak boards.

Thus, the E3 based Ebisu and D3 based Draak boards reliably use 1Gbps and
the speed should be limited to 100Mbps.

Based on work by Kazuya Mizuguchi.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 1 +
 arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 1 +
 2 files changed, 2 insertions(+)

 Based on renesas-devel-20190404-v5.1-rc3

Comments

Wolfram Sang April 8, 2019, 8:41 a.m. UTC | #1 
Hi Simon,

On Mon, Apr 08, 2019 at 10:31:48AM +0200, Simon Horman wrote:
> * According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of
>   August 24, 2018, the TX clock internal delay mode isn't supported
>   on R-Car E3 (r8a77990) and D3 (r8a77995).
> 
> * TX clock internal delay mode is required for reliable 1Gbps communication
>   using the KSZ9031RNX phy present on the Ebisu and Draak boards.
> 
> Thus, the E3 based Ebisu and D3 based Draak boards reliably use 1Gbps and
> the speed should be limited to 100Mbps.

"cannot" missing?

> Based on work by Kazuya Mizuguchi.
> 
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
>  arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 1 +
>  arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 1 +
>  2 files changed, 2 insertions(+)
> 
>  Based on renesas-devel-20190404-v5.1-rc3
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
> index c72772589953..05214b8dd2c5 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
> +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
> @@ -272,6 +272,7 @@
>  		interrupt-parent = <&gpio2>;
>  		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
>  		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
> +		max-speed = <100>;

What about adding a comment explaining this speed limit?

Thanks,

   Wolfram
Simon Horman April 8, 2019, 9:45 a.m. UTC | #2 
On Mon, Apr 08, 2019 at 10:41:43AM +0200, Wolfram Sang wrote:
> Hi Simon,
> 
> On Mon, Apr 08, 2019 at 10:31:48AM +0200, Simon Horman wrote:
> > * According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of
> >   August 24, 2018, the TX clock internal delay mode isn't supported
> >   on R-Car E3 (r8a77990) and D3 (r8a77995).
> > 
> > * TX clock internal delay mode is required for reliable 1Gbps communication
> >   using the KSZ9031RNX phy present on the Ebisu and Draak boards.
> > 
> > Thus, the E3 based Ebisu and D3 based Draak boards reliably use 1Gbps and
> > the speed should be limited to 100Mbps.
> 
> "cannot" missing?

Yes indeed, thanks for noticing.

> > Based on work by Kazuya Mizuguchi.
> > 
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > ---
> >  arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 1 +
> >  arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 1 +
> >  2 files changed, 2 insertions(+)
> > 
> >  Based on renesas-devel-20190404-v5.1-rc3
> > 
> > diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
> > index c72772589953..05214b8dd2c5 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
> > +++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
> > @@ -272,6 +272,7 @@
> >  		interrupt-parent = <&gpio2>;
> >  		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
> >  		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
> > +		max-speed = <100>;
> 
> What about adding a comment explaining this speed limit?

Sure, if you think its worth highlighting in the dts as
well as the changelog.
Wolfram Sang April 8, 2019, 10:56 a.m. UTC | #3 
> > > +		max-speed = <100>;
> > 
> > What about adding a comment explaining this speed limit?
> 
> Sure, if you think its worth highlighting in the dts as
> well as the changelog.

I think this will be helpful for people just getting a tarball of the
kernel and no further history of it. But just 2ยข here, nothing major...
Andrew Lunn April 8, 2019, 9:26 p.m. UTC | #4 
On Mon, Apr 08, 2019 at 10:31:48AM +0200, Simon Horman wrote:
> * According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of
>   August 24, 2018, the TX clock internal delay mode isn't supported
>   on R-Car E3 (r8a77990) and D3 (r8a77995).
> 
> * TX clock internal delay mode is required for reliable 1Gbps communication
>   using the KSZ9031RNX phy present on the Ebisu and Draak boards.

Hi Simon

My reading of the KSZ9031RNX datasheet suggests the PHY can perform
the delays. MMD address 2h, Register 8h - RGMII Clock Pad Skew.

The PHY driver might even have the needed vendor specific DT
properties.

Have you look at using this?

     Andrew
Simon Horman April 10, 2019, 9:27 a.m. UTC | #5 
On Mon, Apr 08, 2019 at 11:26:28PM +0200, Andrew Lunn wrote:
> On Mon, Apr 08, 2019 at 10:31:48AM +0200, Simon Horman wrote:
> > * According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of
> >   August 24, 2018, the TX clock internal delay mode isn't supported
> >   on R-Car E3 (r8a77990) and D3 (r8a77995).
> > 
> > * TX clock internal delay mode is required for reliable 1Gbps communication
> >   using the KSZ9031RNX phy present on the Ebisu and Draak boards.
> 
> Hi Simon
> 
> My reading of the KSZ9031RNX datasheet suggests the PHY can perform
> the delays. MMD address 2h, Register 8h - RGMII Clock Pad Skew.
> 
> The PHY driver might even have the needed vendor specific DT
> properties.
> 
> Have you look at using this?

Thanks for the suggestion Andrew, I will ask Renesas about this.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index c72772589953..05214b8dd2c5 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -272,6 +272,7 @@ 
 		interrupt-parent = <&gpio2>;
 		interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
 		reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+		max-speed = <100>;
 	};
 };
 
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index a7dc11e36fd9..80d82bd047fd 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -175,6 +175,7 @@ 
 		reg = <0>;
 		interrupt-parent = <&gpio5>;
 		interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+		max-speed = <100>;
 	};
 };