| Message ID | 20190410183010.21307-1-mka@chromium.org (mailing list archive) |
|---|---|
| State | Mainlined, archived |
| Commit | 2f60eb2f03b9c3d0a31592c55a88ef62b1403b5d |
| Headers | show |
| Series | ARM: dts: rockchip: Remove unnecessary setting of UART0 SCLK rate on veyron | expand |
Hi, On Wed, Apr 10, 2019 at 11:30 AM Matthias Kaehlcke <mka@chromium.org> wrote: > > Some veyron devices have a Bluetooth controller connected on UART0. > The UART needs to operate at a high speed, however setting the clock > rate at initialization has no practical effect. During initialization > user space adjusts the UART baudrate multiple times, which ends up > changing the SCLK rate. After a successful initiatalization the clk > is running at the desired speed (48MHz). > > Remove the unnecessary clock rate configuration from the DT. > > Signed-off-by: Matthias Kaehlcke <mka@chromium.org> > --- > arch/arm/boot/dts/rk3288-veyron.dtsi | 4 ---- > 1 file changed, 4 deletions(-) Nice. Looks like this hasn't been needed for a while. Back in 3.14 when I first added this it was important because "8250_dw.c" didn't have a clk_set_rate() in it, but seems like it's been there forever now. Reviewed-by: Douglas Anderson <dianders@chromium.org>
Am Mittwoch, 10. April 2019, 20:30:10 CEST schrieb Matthias Kaehlcke: > Some veyron devices have a Bluetooth controller connected on UART0. > The UART needs to operate at a high speed, however setting the clock > rate at initialization has no practical effect. During initialization > user space adjusts the UART baudrate multiple times, which ends up > changing the SCLK rate. After a successful initiatalization the clk > is running at the desired speed (48MHz). > > Remove the unnecessary clock rate configuration from the DT. > > Signed-off-by: Matthias Kaehlcke <mka@chromium.org> applied for 5.2 with Doug's RB. Thanks Heiko
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi index 0bc2409f6903..97e980383e25 100644 --- a/arch/arm/boot/dts/rk3288-veyron.dtsi +++ b/arch/arm/boot/dts/rk3288-veyron.dtsi @@ -378,10 +378,6 @@ &uart0 { status = "okay"; - /* We need to go faster than 24MHz, so adjust clock parents / rates */ - assigned-clocks = <&cru SCLK_UART0>; - assigned-clock-rates = <48000000>; - /* Pins don't include flow control by default; add that in */ pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
Some veyron devices have a Bluetooth controller connected on UART0. The UART needs to operate at a high speed, however setting the clock rate at initialization has no practical effect. During initialization user space adjusts the UART baudrate multiple times, which ends up changing the SCLK rate. After a successful initiatalization the clk is running at the desired speed (48MHz). Remove the unnecessary clock rate configuration from the DT. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> --- arch/arm/boot/dts/rk3288-veyron.dtsi | 4 ---- 1 file changed, 4 deletions(-)