diff mbox series

[v2,10/20] ARM: dts: r8a77470: Add FDP1 support

Message ID 1554969262-15028-11-git-send-email-cv-dong@jinso.co.jp (mailing list archive)
State Changes Requested
Delegated to: Simon Horman
Headers show
Series Add more support to the RZ/G1C (r8a77470) SoC | expand

Commit Message

Cao Van Dong April 11, 2019, 7:54 a.m. UTC 
Add fdp1 node to dtsi for FDP1 support on the RZ/G1C (r8a77470) SoC.

Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp>
---
 arch/arm/boot/dts/r8a77470.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

Comments

Simon Horman April 12, 2019, 11:45 a.m. UTC | #1 
Hi Dong-san,

On Thu, Apr 11, 2019 at 04:54:12PM +0900, Cao Van Dong wrote:
> Add fdp1 node to dtsi for FDP1 support on the RZ/G1C (r8a77470) SoC.
> 
> Signed-off-by: Cao Van Dong <cv-dong@jinso.co.jp>
> ---
>  arch/arm/boot/dts/r8a77470.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
> index 2540bca..7881516 100644
> --- a/arch/arm/boot/dts/r8a77470.dtsi
> +++ b/arch/arm/boot/dts/r8a77470.dtsi
> @@ -1131,6 +1131,15 @@
>  			resets = <&cpg 128>;
>  		};
>  
> +		fdp1@fe940000 {
> +			compatible = "renesas,fdp1";
> +			reg = <0 0xfe940000 0 0x2400>;
> +			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg CPG_MOD 119>;
> +			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
> +			resets = <&cpg 119>;
> +		};
> +

Nodes should be sorted by
1. Bus address
2. IP block tupe

So the above vsp nodes should not go before sd@ee100000.

Otherwise this patch looks good to me.

>  		sdhi0: sd@ee100000 {
>  			compatible = "renesas,sdhi-r8a77470",
>  				     "renesas,rcar-gen2-sdhi";
> -- 
> 2.7.4
>
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi
index 2540bca..7881516 100644
--- a/arch/arm/boot/dts/r8a77470.dtsi
+++ b/arch/arm/boot/dts/r8a77470.dtsi
@@ -1131,6 +1131,15 @@ 
 			resets = <&cpg 128>;
 		};
 
+		fdp1@fe940000 {
+			compatible = "renesas,fdp1";
+			reg = <0 0xfe940000 0 0x2400>;
+			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 119>;
+			power-domains = <&sysc R8A77470_PD_ALWAYS_ON>;
+			resets = <&cpg 119>;
+		};
+
 		sdhi0: sd@ee100000 {
 			compatible = "renesas,sdhi-r8a77470",
 				     "renesas,rcar-gen2-sdhi";