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[1/3] drm/i915: Shortcut readiness to reset check

Message ID 20190412153723.31931-1-mika.kuoppala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series [1/3] drm/i915: Shortcut readiness to reset check | expand

Commit Message

Mika Kuoppala April 12, 2019, 3:37 p.m. UTC
If the engine says it is ready for reset, it is ready
so avoid further dancing and proceed.

Cc: Chris Wilson <chris@chris-wilson.co.uk
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reset.c | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Chris Wilson April 12, 2019, 3:51 p.m. UTC | #1
Quoting Mika Kuoppala (2019-04-12 16:37:21)
> If the engine says it is ready for reset, it is ready
> so avoid further dancing and proceed.
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reset.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c
> index 68875ba43b8d..cde1a5309336 100644
> --- a/drivers/gpu/drm/i915/i915_reset.c
> +++ b/drivers/gpu/drm/i915/i915_reset.c
> @@ -490,8 +490,13 @@ static int gen11_reset_engines(struct drm_i915_private *i915,
>  static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
>  {
>         struct intel_uncore *uncore = engine->uncore;
> +       u32 ctl;
>         int ret;
>  
> +       ctl = intel_uncore_read_fw(uncore, RING_RESET_CTL(engine->mmio_base));
> +       if (ctl & RESET_CTL_READY_TO_RESET)
> +               return 0;
> +

Would seem to not matter atm, but it does make the next patch easier.
How about pulling the i915_reg_t into this, so the second is more about
merging the CAT_ERROR handling?
-Chris
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c
index 68875ba43b8d..cde1a5309336 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -490,8 +490,13 @@  static int gen11_reset_engines(struct drm_i915_private *i915,
 static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
 {
 	struct intel_uncore *uncore = engine->uncore;
+	u32 ctl;
 	int ret;
 
+	ctl = intel_uncore_read_fw(uncore, RING_RESET_CTL(engine->mmio_base));
+	if (ctl & RESET_CTL_READY_TO_RESET)
+		return 0;
+
 	intel_uncore_write_fw(uncore,
 			      RING_RESET_CTL(engine->mmio_base),
 			      _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));