diff mbox series

[2/2] drm/i915: Handle catastrophic error on engine reset

Message ID 20190412165353.16432-1-mika.kuoppala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series [1/2] drm/i915: Shortcut readiness to reset check | expand

Commit Message

Mika Kuoppala April 12, 2019, 4:53 p.m. UTC 
If cat error is set, we need to clear it by acking it. Further,
if it is set, we must not do a normal request for reset.

v2: avoid goto (Chris)
v3: comment, error format, direct assign (Chris)
Bspec: 12567
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h   |  6 ++++--
 drivers/gpu/drm/i915/i915_reset.c | 18 ++++++++++++++++--
 2 files changed, 20 insertions(+), 4 deletions(-)

Comments

Chris Wilson April 12, 2019, 4:56 p.m. UTC | #1 
Quoting Mika Kuoppala (2019-04-12 17:53:53)
> If cat error is set, we need to clear it by acking it. Further,
> if it is set, we must not do a normal request for reset.
> 
> v2: avoid goto (Chris)
> v3: comment, error format, direct assign (Chris)
> Bspec: 12567
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Lgtm,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Now if we only knew of a source of catastrophic errors...
-Chris
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8ad2f0a03f28..c1c0f7ab03e9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2446,8 +2446,10 @@  enum i915_power_well_id {
 #define RING_HWS_PGA(base)	_MMIO((base) + 0x80)
 #define RING_HWS_PGA_GEN6(base)	_MMIO((base) + 0x2080)
 #define RING_RESET_CTL(base)	_MMIO((base) + 0xd0)
-#define   RESET_CTL_REQUEST_RESET  (1 << 0)
-#define   RESET_CTL_READY_TO_RESET (1 << 1)
+#define   RESET_CTL_CAT_ERROR	   REG_BIT(2)
+#define   RESET_CTL_READY_TO_RESET REG_BIT(1)
+#define   RESET_CTL_REQUEST_RESET  REG_BIT(0)
+
 #define RING_SEMA_WAIT_POLL(base) _MMIO((base) + 0x24c)
 
 #define HSW_GTT_CACHE_EN	_MMIO(0x4024)
diff --git a/drivers/gpu/drm/i915/i915_reset.c b/drivers/gpu/drm/i915/i915_reset.c
index ab628a8f6c1f..8707effc29c4 100644
--- a/drivers/gpu/drm/i915/i915_reset.c
+++ b/drivers/gpu/drm/i915/i915_reset.c
@@ -495,7 +495,19 @@  static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
 	int ret;
 
 	ctl = intel_uncore_read_fw(uncore, reg);
-	if (!(ctl & RESET_CTL_READY_TO_RESET)) {
+
+	if (ctl & RESET_CTL_CAT_ERROR) {
+		request = RESET_CTL_CAT_ERROR;
+		mask = RESET_CTL_CAT_ERROR;
+
+		/* Catastrophic errors need to be cleared */
+		ack = 0;
+
+		/*
+		 * For cat errors, ready for reset sequence
+		 * needs to be bypassed: HAS#396813
+		 */
+	} else if (!(ctl & RESET_CTL_READY_TO_RESET)) {
 		request = RESET_CTL_REQUEST_RESET;
 		mask = RESET_CTL_READY_TO_RESET;
 		ack = RESET_CTL_READY_TO_RESET;
@@ -508,7 +520,9 @@  static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
 	ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
 					   700, 0, NULL);
 	if (ret)
-		DRM_ERROR("%s: reset request timeout\n", engine->name);
+		DRM_ERROR("%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n",
+			  engine->name, request,
+			  intel_uncore_read_fw(uncore, reg));
 
 	return ret;
 }