| Message ID | 20190415210031.54062-1-rrangel@chromium.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1] mmc: core: Verify SD bus width | expand |
On Mon, Apr 15, 2019 at 03:00:31PM -0600, Raul E Rangel wrote: > The SD Physical Layer Spec says the following: Since the SD Memory Card > shall support at least the two bus modes 1-bit or 4-bit width, then any SD > Card shall set at least bits 0 and 2 (SD_BUS_WIDTH="0101"). > > This change verifies the card has specified a bus width. > > verified it didn't mount. > > Signed-off-by: Raul E Rangel <rrangel@chromium.org> > --- > AMD SDHC Device 7806 can get into a bad state after a card disconnect > where anything transferred via the DATA lines will always result in a > zero filled buffer. Currently the driver will continue without error if > the HC is in this condition. A block device will be created, but reading > from it will result in a zero buffer. This makes it seem like the SD > device has been erased, when in actuality the data is never getting > copied from the DATA lines to the data buffer. > > SCR is the first command in the SD initialization sequence that uses the > DATA lines. By checking that the response was invalid, we can abort > mounting the card. > > Here is an example of a bad trace: https://pastebin.com/TY2cF9n0 > Look for sd_scr and sd_ssr. Personally I think that all the info you have here below the --- should be in the actual commit message. It provides context for the bug that the patch is fixing, what the old and new behaviors are and how you tested. The text below the --- is for ephemeral things that don't matter once the code is committed: what revision of the patch set you are on, noting that you've addressed someone's comments, etc.
> > The SD Physical Layer Spec says the following: Since the SD Memory Card > shall support at least the two bus modes 1-bit or 4-bit width, then any SD > Card shall set at least bits 0 and 2 (SD_BUS_WIDTH="0101"). > > This change verifies the card has specified a bus width. > > verified it didn't mount. > > Signed-off-by: Raul E Rangel <rrangel@chromium.org> Acked-by: Avri Altman <avri.altman@wdc.com> > --- > AMD SDHC Device 7806 can get into a bad state after a card disconnect > where anything transferred via the DATA lines will always result in a > zero filled buffer. Currently the driver will continue without error if > the HC is in this condition. A block device will be created, but reading > from it will result in a zero buffer. This makes it seem like the SD > device has been erased, when in actuality the data is never getting > copied from the DATA lines to the data buffer. > > SCR is the first command in the SD initialization sequence that uses the > DATA lines. By checking that the response was invalid, we can abort > mounting the card. > > Here is an example of a bad trace: https://pastebin.com/TY2cF9n0 > Look for sd_scr and sd_ssr. > > drivers/mmc/core/sd.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c > index 265e1aeeb9d8..f6481f8e9fe7 100644 > --- a/drivers/mmc/core/sd.c > +++ b/drivers/mmc/core/sd.c > @@ -205,6 +205,13 @@ static int mmc_decode_scr(struct mmc_card *card) > > scr->sda_vsn = UNSTUFF_BITS(resp, 56, 4); > scr->bus_widths = UNSTUFF_BITS(resp, 48, 4); > + > + /* SD Spec says: any SD Card shall set at least bits 0 and 2 */ > + if (!scr->bus_widths) { So why not testing that exact mask? you have SD_SCR_BUS_WIDTH_1 and SD_SCR_BUS_WIDTH_4 already defined...
diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c index 265e1aeeb9d8..f6481f8e9fe7 100644 --- a/drivers/mmc/core/sd.c +++ b/drivers/mmc/core/sd.c @@ -205,6 +205,13 @@ static int mmc_decode_scr(struct mmc_card *card) scr->sda_vsn = UNSTUFF_BITS(resp, 56, 4); scr->bus_widths = UNSTUFF_BITS(resp, 48, 4); + + /* SD Spec says: any SD Card shall set at least bits 0 and 2 */ + if (!scr->bus_widths) { + pr_err("%s: invalid bus width\n", mmc_hostname(card->host)); + return -EINVAL; + } + if (scr->sda_vsn == SCR_SPEC_VER_2) /* Check if Physical Layer Spec v3.0 is supported */ scr->sda_spec3 = UNSTUFF_BITS(resp, 47, 1);
The SD Physical Layer Spec says the following: Since the SD Memory Card shall support at least the two bus modes 1-bit or 4-bit width, then any SD Card shall set at least bits 0 and 2 (SD_BUS_WIDTH="0101"). This change verifies the card has specified a bus width. verified it didn't mount. Signed-off-by: Raul E Rangel <rrangel@chromium.org> --- AMD SDHC Device 7806 can get into a bad state after a card disconnect where anything transferred via the DATA lines will always result in a zero filled buffer. Currently the driver will continue without error if the HC is in this condition. A block device will be created, but reading from it will result in a zero buffer. This makes it seem like the SD device has been erased, when in actuality the data is never getting copied from the DATA lines to the data buffer. SCR is the first command in the SD initialization sequence that uses the DATA lines. By checking that the response was invalid, we can abort mounting the card. Here is an example of a bad trace: https://pastebin.com/TY2cF9n0 Look for sd_scr and sd_ssr. drivers/mmc/core/sd.c | 7 +++++++ 1 file changed, 7 insertions(+)