| Message ID | 20190225065112.3400-1-seiya.wang@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/2] arm64: dts: mt8173: correct cpu type of cpu2 and cpu3 to cortex-a72 | expand |
On Mon, 2019-02-25 at 14:51 +0800, Seiya Wang wrote: > The cpu type of cpu2 and cpu3 should be cortex-a72, not cortex-a57. > > Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > index 44374c506a1c..99675c51577a 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > @@ -178,12 +178,12 @@ > > cpu2: cpu@100 { > device_type = "cpu"; > - compatible = "arm,cortex-a57"; > + compatible = "arm,cortex-a72"; > reg = <0x100>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > #cooling-cells = <2>; > - clocks = <&infracfg CLK_INFRA_CA57SEL>, > + clocks = <&infracfg CLK_INFRA_CA72SEL>, > <&apmixedsys CLK_APMIXED_MAINPLL>; > clock-names = "cpu", "intermediate"; > operating-points-v2 = <&cluster1_opp>; > @@ -191,12 +191,12 @@ > > cpu3: cpu@101 { > device_type = "cpu"; > - compatible = "arm,cortex-a57"; > + compatible = "arm,cortex-a72"; > reg = <0x101>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > #cooling-cells = <2>; > - clocks = <&infracfg CLK_INFRA_CA57SEL>, > + clocks = <&infracfg CLK_INFRA_CA72SEL>, > <&apmixedsys CLK_APMIXED_MAINPLL>; > clock-names = "cpu", "intermediate"; > operating-points-v2 = <&cluster1_opp>; Since CLK_INFRA_CA72SEL has been added in mt8173-clk.h , please review this patch. Thanks.
On 25/02/2019 07:51, Seiya Wang wrote: > The cpu type of cpu2 and cpu3 should be cortex-a72, not cortex-a57. > > Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > applied to v5.1-next/dts64 Sorry for the late answer. > diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > index 44374c506a1c..99675c51577a 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi > @@ -178,12 +178,12 @@ > > cpu2: cpu@100 { > device_type = "cpu"; > - compatible = "arm,cortex-a57"; > + compatible = "arm,cortex-a72"; > reg = <0x100>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > #cooling-cells = <2>; > - clocks = <&infracfg CLK_INFRA_CA57SEL>, > + clocks = <&infracfg CLK_INFRA_CA72SEL>, > <&apmixedsys CLK_APMIXED_MAINPLL>; > clock-names = "cpu", "intermediate"; > operating-points-v2 = <&cluster1_opp>; > @@ -191,12 +191,12 @@ > > cpu3: cpu@101 { > device_type = "cpu"; > - compatible = "arm,cortex-a57"; > + compatible = "arm,cortex-a72"; > reg = <0x101>; > enable-method = "psci"; > cpu-idle-states = <&CPU_SLEEP_0>; > #cooling-cells = <2>; > - clocks = <&infracfg CLK_INFRA_CA57SEL>, > + clocks = <&infracfg CLK_INFRA_CA72SEL>, > <&apmixedsys CLK_APMIXED_MAINPLL>; > clock-names = "cpu", "intermediate"; > operating-points-v2 = <&cluster1_opp>; >
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 44374c506a1c..99675c51577a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -178,12 +178,12 @@ cpu2: cpu@100 { device_type = "cpu"; - compatible = "arm,cortex-a57"; + compatible = "arm,cortex-a72"; reg = <0x100>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; #cooling-cells = <2>; - clocks = <&infracfg CLK_INFRA_CA57SEL>, + clocks = <&infracfg CLK_INFRA_CA72SEL>, <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster1_opp>; @@ -191,12 +191,12 @@ cpu3: cpu@101 { device_type = "cpu"; - compatible = "arm,cortex-a57"; + compatible = "arm,cortex-a72"; reg = <0x101>; enable-method = "psci"; cpu-idle-states = <&CPU_SLEEP_0>; #cooling-cells = <2>; - clocks = <&infracfg CLK_INFRA_CA57SEL>, + clocks = <&infracfg CLK_INFRA_CA72SEL>, <&apmixedsys CLK_APMIXED_MAINPLL>; clock-names = "cpu", "intermediate"; operating-points-v2 = <&cluster1_opp>;
The cpu type of cpu2 and cpu3 should be cortex-a72, not cortex-a57. Signed-off-by: Seiya Wang <seiya.wang@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)