Message ID | 1555324408-26054-11-git-send-email-swati2.sharma@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | drm/i915: adding state checker for gamma lut values | expand |
On Mon, 15 Apr 2019, Swati Sharma <swati2.sharma@intel.com> wrote: > Signed-off-by: Swati Sharma <swati2.sharma@intel.com> Please add a commit message, and make this patch #2 in the series after the changes I suggested in patch #1. BR, Jani. > --- > drivers/gpu/drm/i915/intel_display.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index f29a348..0fc9dab 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -8275,6 +8275,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, > pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe)); > > i9xx_get_pipe_color_config(pipe_config); > + intel_get_color_config(pipe_config); > > if (INTEL_GEN(dev_priv) < 4) > pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; > @@ -9348,6 +9349,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc, > pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe)); > > i9xx_get_pipe_color_config(pipe_config); > + intel_get_color_config(pipe_config); > > if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { > struct intel_shared_dpll *pll; > @@ -10011,6 +10013,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, > pipe_config->csc_enable = true; > } else { > i9xx_get_pipe_color_config(pipe_config); > + intel_get_color_config(pipe_config); > } > > power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f29a348..0fc9dab 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -8275,6 +8275,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, pipe_config->cgm_mode = I915_READ(CGM_PIPE_MODE(crtc->pipe)); i9xx_get_pipe_color_config(pipe_config); + intel_get_color_config(pipe_config); if (INTEL_GEN(dev_priv) < 4) pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; @@ -9348,6 +9349,7 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc, pipe_config->csc_mode = I915_READ(PIPE_CSC_MODE(crtc->pipe)); i9xx_get_pipe_color_config(pipe_config); + intel_get_color_config(pipe_config); if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { struct intel_shared_dpll *pll; @@ -10011,6 +10013,7 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc, pipe_config->csc_enable = true; } else { i9xx_get_pipe_color_config(pipe_config); + intel_get_color_config(pipe_config); } power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
Signed-off-by: Swati Sharma <swati2.sharma@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 3 +++ 1 file changed, 3 insertions(+)