| Message ID | 1555683568-20882-2-git-send-email-l.luba@partner.samsung.com (mailing list archive) |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | Exynos5 Dynamic Memory Controller driver | expand |
Hi, On 19. 4. 19. 오후 11:19, Lukasz Luba wrote: > Define new IDs for clocks used by Dynamic Memory Controller in > Exynos5422 SoC. > > Acked-by: Rob Herring <robh@kernel.org> > Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> > --- > include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++- > 1 file changed, 17 insertions(+), 1 deletion(-) > > diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h > index 355f469..abb1842 100644 > --- a/include/dt-bindings/clock/exynos5420.h > +++ b/include/dt-bindings/clock/exynos5420.h > @@ -60,6 +60,7 @@ > #define CLK_MAU_EPLL 159 > #define CLK_SCLK_HSIC_12M 160 > #define CLK_SCLK_MPHY_IXTAL24 161 > +#define CLK_SCLK_BPLL 162 > > /* gate clocks */ > #define CLK_UART0 257 > @@ -195,6 +196,18 @@ > #define CLK_ACLK432_CAM 518 > #define CLK_ACLK_FL1550_CAM 519 > #define CLK_ACLK550_CAM 520 > +#define CLK_CLKM_PHY0 521 > +#define CLK_CLKM_PHY1 522 > +#define CLK_ACLK_PPMU_DREX0_0 523 > +#define CLK_ACLK_PPMU_DREX0_1 524 > +#define CLK_ACLK_PPMU_DREX1_0 525 > +#define CLK_ACLK_PPMU_DREX1_1 526 > +#define CLK_PCLK_PPMU_DREX0_0 527 > +#define CLK_PCLK_PPMU_DREX0_1 528 > +#define CLK_PCLK_PPMU_DREX1_0 529 > +#define CLK_PCLK_PPMU_DREX1_1 530 > +#define CLK_CDREX_PAUSE 531 > +#define CLK_CDREX_TIMING_SET 532 I cannot find the usage code of both CLK_CDREX_PAUSE and CLK_CDREX_TIMING_SET in these patchset. Please remove them. (snip)
Hi Chanwoo, On 4/30/19 6:47 AM, Chanwoo Choi wrote: > Hi, > > On 19. 4. 19. 오후 11:19, Lukasz Luba wrote: >> Define new IDs for clocks used by Dynamic Memory Controller in >> Exynos5422 SoC. >> >> Acked-by: Rob Herring <robh@kernel.org> >> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> >> --- >> include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++- >> 1 file changed, 17 insertions(+), 1 deletion(-) >> >> diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h >> index 355f469..abb1842 100644 >> --- a/include/dt-bindings/clock/exynos5420.h >> +++ b/include/dt-bindings/clock/exynos5420.h >> @@ -60,6 +60,7 @@ >> #define CLK_MAU_EPLL 159 >> #define CLK_SCLK_HSIC_12M 160 >> #define CLK_SCLK_MPHY_IXTAL24 161 >> +#define CLK_SCLK_BPLL 162 >> >> /* gate clocks */ >> #define CLK_UART0 257 >> @@ -195,6 +196,18 @@ >> #define CLK_ACLK432_CAM 518 >> #define CLK_ACLK_FL1550_CAM 519 >> #define CLK_ACLK550_CAM 520 >> +#define CLK_CLKM_PHY0 521 >> +#define CLK_CLKM_PHY1 522 >> +#define CLK_ACLK_PPMU_DREX0_0 523 >> +#define CLK_ACLK_PPMU_DREX0_1 524 >> +#define CLK_ACLK_PPMU_DREX1_0 525 >> +#define CLK_ACLK_PPMU_DREX1_1 526 >> +#define CLK_PCLK_PPMU_DREX0_0 527 >> +#define CLK_PCLK_PPMU_DREX0_1 528 >> +#define CLK_PCLK_PPMU_DREX1_0 529 >> +#define CLK_PCLK_PPMU_DREX1_1 530 >> +#define CLK_CDREX_PAUSE 531 >> +#define CLK_CDREX_TIMING_SET 532 > > I cannot find the usage code of both CLK_CDREX_PAUSE > and CLK_CDREX_TIMING_SET in these patchset. Thank you for this catch. I will remove them. Regards, Lukasz > > Please remove them. > > (snip) >
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 355f469..abb1842 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -60,6 +60,7 @@ #define CLK_MAU_EPLL 159 #define CLK_SCLK_HSIC_12M 160 #define CLK_SCLK_MPHY_IXTAL24 161 +#define CLK_SCLK_BPLL 162 /* gate clocks */ #define CLK_UART0 257 @@ -195,6 +196,18 @@ #define CLK_ACLK432_CAM 518 #define CLK_ACLK_FL1550_CAM 519 #define CLK_ACLK550_CAM 520 +#define CLK_CLKM_PHY0 521 +#define CLK_CLKM_PHY1 522 +#define CLK_ACLK_PPMU_DREX0_0 523 +#define CLK_ACLK_PPMU_DREX0_1 524 +#define CLK_ACLK_PPMU_DREX1_0 525 +#define CLK_ACLK_PPMU_DREX1_1 526 +#define CLK_PCLK_PPMU_DREX0_0 527 +#define CLK_PCLK_PPMU_DREX0_1 528 +#define CLK_PCLK_PPMU_DREX1_0 529 +#define CLK_PCLK_PPMU_DREX1_1 530 +#define CLK_CDREX_PAUSE 531 +#define CLK_CDREX_TIMING_SET 532 /* mux clocks */ #define CLK_MOUT_HDMI 640 @@ -217,6 +230,8 @@ #define CLK_MOUT_EPLL 657 #define CLK_MOUT_MAU_EPLL 658 #define CLK_MOUT_USER_MAU_EPLL 659 +#define CLK_MOUT_SCLK_SPLL 660 +#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661 /* divider clocks */ #define CLK_DOUT_PIXEL 768 @@ -248,8 +263,9 @@ #define CLK_DOUT_CCLK_DREX0 794 #define CLK_DOUT_CLK2X_PHY0 795 #define CLK_DOUT_PCLK_CORE_MEM 796 +#define CLK_FF_DOUT_SPLL2 797 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 797 +#define CLK_NR_CLKS 798 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */