| Message ID | 20190508115605.13726-1-horms+renesas@verge.net.au (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Simon Horman |
| Headers | show |
| Series | [v2] arm64: dts: renesas: r8a7795: Create thermal zone to support IPA | expand |
Hi Simon, Thanks for your patch! On Wed, May 8, 2019 at 1:56 PM Simon Horman <horms+renesas@verge.net.au> wrote: > From: Dien Pham <dien.pham.ry@renesas.com> > > Setup a thermal zone driven by SoC temperature sensor. > Create passive trip points and bind them to CPUFreq cooling > device that supports power extension. > > In R-Car Gen3, IPA is supported for only one channel > (on H3/M3/M3N board, it is channel THS3). Reason: > Currently, IPA controls base on only CPU temperature. > And only one thermal channel is assembled closest > CPU cores is selected as target of IPA. > If other channels are used, IPA controlling is not properly. > > The device supports 5 cooling states which can be categorised as follows: > > 0 & 1) boost (clocking up) > 2) default > 3 & 4) cooling (clocking down) > > Currently the thermal framework assumes that the default is the minimum, > or in other words there is no provision for handling boost states. > So this patch only describes the upper 3 states, default and cooling. > > A single cooling device is described for all A57 CPUs as this > reflects that physically there is only one cooling device present. > > This patch improves on an earlier version by: > > * Omitting cooling-max-level and cooling-min-level properties which > are no longer present in mainline as of v4.17 > * Removing an unused trip-point0 node sub-property from the trips > property. > * Using cooling-device indexes such that maximum refers to maximum cooling > rather than the inverse. > > The long signed-off by chain below reflects many revisions, mainly > internal, that this patch has been through. > > Signed-off-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> > Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com> > Signed-off-by: Hien Dang <hien.dang.eb@rvc.renesas.com> > Signed-off-by: An Huynh <an.huynh.uj@rvc.renesas.com> > Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> > Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> > Signed-off-by: Simon Horman <simon.horman@netronome.com> Did you intend to use this SoB value? > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > @@ -155,6 +155,7 @@ > power-domains = <&sysc R8A7795_PD_CA57_CPU0>; > next-level-cache = <&L2_CA57>; > enable-method = "psci"; > + dynamic-power-coefficient = <854>; The dynamic-power-coefficient property is a property of the CPU, documented in Documentation/devicetree/bindings/arm/cpus.yaml, and not directly related to thermal zones. Hence I think its addition should be done in a separate patch. > clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; > operating-points-v2 = <&cluster0_opp>; > capacity-dmips-mhz = <1024>; > @@ -207,6 +208,8 @@ > power-domains = <&sysc R8A7795_PD_CA53_CPU0>; > next-level-cache = <&L2_CA53>; > enable-method = "psci"; > + #cooling-cells = <2>; > + dynamic-power-coefficient = <277>; Likewise. > clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; > operating-points-v2 = <&cluster1_opp>; > capacity-dmips-mhz = <535>; Gr{oetje,eeting}s, Geert
On Wed, May 08, 2019 at 03:20:03PM +0200, Geert Uytterhoeven wrote: > Hi Simon, > > Thanks for your patch! > > On Wed, May 8, 2019 at 1:56 PM Simon Horman <horms+renesas@verge.net.au> wrote: ... > > > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > > @@ -155,6 +155,7 @@ > > power-domains = <&sysc R8A7795_PD_CA57_CPU0>; > > next-level-cache = <&L2_CA57>; > > enable-method = "psci"; > > + dynamic-power-coefficient = <854>; > > The dynamic-power-coefficient property is a property of the CPU, > documented in Documentation/devicetree/bindings/arm/cpus.yaml, > and not directly related to thermal zones. > > Hence I think its addition should be done in a separate patch. Sure, can do. Should the coefficient be added to each CPU or only to a57_0 and a53_0, as is the case in this patch? I assume the latter because the A53 coefficient applies to all A53 cores and likewise for A57. > > clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; > > operating-points-v2 = <&cluster0_opp>; > > capacity-dmips-mhz = <1024>; > > @@ -207,6 +208,8 @@ > > power-domains = <&sysc R8A7795_PD_CA53_CPU0>; > > next-level-cache = <&L2_CA53>; > > enable-method = "psci"; > > + #cooling-cells = <2>; > > + dynamic-power-coefficient = <277>; > > Likewise. > > > clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; > > operating-points-v2 = <&cluster1_opp>; > > capacity-dmips-mhz = <535>; > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds >
Hi Simon, On Thu, May 9, 2019 at 11:57 AM Simon Horman <horms@verge.net.au> wrote: > On Wed, May 08, 2019 at 03:20:03PM +0200, Geert Uytterhoeven wrote: > > On Wed, May 8, 2019 at 1:56 PM Simon Horman <horms+renesas@verge.net.au> wrote: > > > --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi > > > +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi > > > @@ -155,6 +155,7 @@ > > > power-domains = <&sysc R8A7795_PD_CA57_CPU0>; > > > next-level-cache = <&L2_CA57>; > > > enable-method = "psci"; > > > + dynamic-power-coefficient = <854>; > > > > The dynamic-power-coefficient property is a property of the CPU, > > documented in Documentation/devicetree/bindings/arm/cpus.yaml, > > and not directly related to thermal zones. > > > > Hence I think its addition should be done in a separate patch. > > Sure, can do. Should the coefficient be added to each CPU or only > to a57_0 and a53_0, as is the case in this patch? > > I assume the latter because the A53 coefficient applies to all A53 cores > and likewise for A57. The latter, I think. > > > clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; > > > operating-points-v2 = <&cluster0_opp>; > > > capacity-dmips-mhz = <1024>; > > > @@ -207,6 +208,8 @@ > > > power-domains = <&sysc R8A7795_PD_CA53_CPU0>; > > > next-level-cache = <&L2_CA53>; > > > enable-method = "psci"; > > > + #cooling-cells = <2>; > > > + dynamic-power-coefficient = <277>; > > > > Likewise. > > > > > clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; > > > operating-points-v2 = <&cluster1_opp>; > > > capacity-dmips-mhz = <535>; Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index abeac3059383..41111dcf80ae 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -155,6 +155,7 @@ power-domains = <&sysc R8A7795_PD_CA57_CPU0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; + dynamic-power-coefficient = <854>; clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; operating-points-v2 = <&cluster0_opp>; capacity-dmips-mhz = <1024>; @@ -207,6 +208,8 @@ power-domains = <&sysc R8A7795_PD_CA53_CPU0>; next-level-cache = <&L2_CA53>; enable-method = "psci"; + #cooling-cells = <2>; + dynamic-power-coefficient = <277>; clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; operating-points-v2 = <&cluster1_opp>; capacity-dmips-mhz = <535>; @@ -3098,58 +3101,30 @@ polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 0>; + sustainable-power = <6313>; trips { - sensor1_passive: sensor1-passive { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; sensor1_crit: sensor1-crit { temperature = <120000>; hysteresis = <1000>; type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&sensor1_passive>; - cooling-device = <&a57_0 4 4>, - <&a57_1 4 4>, - <&a57_2 4 4>, - <&a57_3 4 4>; - }; - }; }; sensor_thermal2: sensor-thermal2 { polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsc 1>; + sustainable-power = <6313>; trips { - sensor2_passive: sensor2-passive { - temperature = <95000>; - hysteresis = <1000>; - type = "passive"; - }; sensor2_crit: sensor2-crit { temperature = <120000>; hysteresis = <1000>; type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&sensor2_passive>; - cooling-device = <&a57_0 4 4>, - <&a57_1 4 4>, - <&a57_2 4 4>, - <&a57_3 4 4>; - }; - }; }; sensor_thermal3: sensor-thermal3 { @@ -3158,11 +3133,12 @@ thermal-sensors = <&tsc 2>; trips { - sensor3_passive: sensor3-passive { - temperature = <95000>; + target: trip-point1 { + temperature = <100000>; hysteresis = <1000>; type = "passive"; }; + sensor3_crit: sensor3-crit { temperature = <120000>; hysteresis = <1000>; @@ -3172,11 +3148,15 @@ cooling-maps { map0 { - trip = <&sensor3_passive>; - cooling-device = <&a57_0 4 4>, - <&a57_1 4 4>, - <&a57_2 4 4>, - <&a57_3 4 4>; + trip = <&target>; + cooling-device = <&a57_0 2 4>; + contribution = <1024>; + }; + + map1 { + trip = <&target>; + cooling-device = <&a53_0 0 2>; + contribution = <1024>; }; }; };