| Message ID | 20190513091548.16674-1-narmstrong@baylibre.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | mmc: meson-gx: add ddr-access-quirk support | expand |
On Mon, 2019-05-13 at 11:15 +0200, Neil Armstrong wrote: > On the Amlogic G12A SoC family, (only) the SDIO controller fails to access > the data from DDR, leading to a broken controller. > > Add the amlogic,ddr-access-quirk property so signal this particular > controller has this bug and needs a quirk to work properly. > > But each MMC controller has 1,5KiB of SRAM after the registers, that can > be used as bounce buffer to avoid direct DDR access from the integrated > DMAs (this SRAM may be used by the boot ROM when DDR is not yet initialized). > > The quirk is to disable the chained descriptor for this controller, and > use this SRAM memory zone as buffer for the bounce buffer fallback mode. > > The performance hit hasn't been evaluated, but the fix has been tested > using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave > 55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed > at 50MHz clock. It gave around 170 Mbits/sec as SDR104 and 200MHz clock. These numbers looks to be limited by the MMC bandwidth of the related modes. So, if the SRAM quirk introduce a penalty for the controller, it does not appear to be a limiting factor, AFAICT. > > Neil Armstrong (3): > dt-bindings: mmc: meson-gx: add ddr-access-quirk property > mmc: meson-gx: add ddr-access-quirk > arm64: dts: meson-g12a: add ddr-access-quirk property to SDIO > controller > > .../bindings/mmc/amlogic,meson-gx.txt | 4 ++ > arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 + > drivers/mmc/host/meson-gx-mmc.c | 65 +++++++++++++++---- > 3 files changed, 57 insertions(+), 13 deletions(-) >
On Mon, 2019-05-13 at 11:58 +0200, Jerome Brunet wrote: > > The performance hit hasn't been evaluated, but the fix has been tested > > using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave > > 55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed > > at 50MHz clock. It gave around 170 Mbits/sec as SDR104 and 200MHz clock. > > These numbers looks to be limited by the MMC bandwidth of the related modes. > So, if the SRAM quirk introduce a penalty for the controller, it does not appear > to be a limiting factor, AFAICT. Got confused. This comment is completely wrong, please ignore
On 5/13/19 11:15 AM, Neil Armstrong wrote: > On the Amlogic G12A SoC family, (only) the SDIO controller fails to access > the data from DDR, leading to a broken controller. > > Add the amlogic,ddr-access-quirk property so signal this particular > controller has this bug and needs a quirk to work properly. > > But each MMC controller has 1,5KiB of SRAM after the registers, that can > be used as bounce buffer to avoid direct DDR access from the integrated > DMAs (this SRAM may be used by the boot ROM when DDR is not yet initialized). > > The quirk is to disable the chained descriptor for this controller, and > use this SRAM memory zone as buffer for the bounce buffer fallback mode. > > The performance hit hasn't been evaluated, but the fix has been tested > using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave > 55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed > at 50MHz clock. It gave around 170 Mbits/sec as SDR104 and 200MHz clock. > > Neil Armstrong (3): > dt-bindings: mmc: meson-gx: add ddr-access-quirk property > mmc: meson-gx: add ddr-access-quirk > arm64: dts: meson-g12a: add ddr-access-quirk property to SDIO > controller > > .../bindings/mmc/amlogic,meson-gx.txt | 4 ++ > arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 + > drivers/mmc/host/meson-gx-mmc.c | 65 +++++++++++++++---- > 3 files changed, 57 insertions(+), 13 deletions(-) > Test with SEI510 board no problem or regression seen Tested-by: Guillaume La Roque <glaroque@baylibre.com>
On the Amlogic G12A SoC family, (only) the SDIO controller fails to access the data from DDR, leading to a broken controller. Add the amlogic,ddr-access-quirk property so signal this particular controller has this bug and needs a quirk to work properly. But each MMC controller has 1,5KiB of SRAM after the registers, that can be used as bounce buffer to avoid direct DDR access from the integrated DMAs (this SRAM may be used by the boot ROM when DDR is not yet initialized). The quirk is to disable the chained descriptor for this controller, and use this SRAM memory zone as buffer for the bounce buffer fallback mode. The performance hit hasn't been evaluated, but the fix has been tested using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave 55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed at 50MHz clock. It gave around 170 Mbits/sec as SDR104 and 200MHz clock. Neil Armstrong (3): dt-bindings: mmc: meson-gx: add ddr-access-quirk property mmc: meson-gx: add ddr-access-quirk arm64: dts: meson-g12a: add ddr-access-quirk property to SDIO controller .../bindings/mmc/amlogic,meson-gx.txt | 4 ++ arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 + drivers/mmc/host/meson-gx-mmc.c | 65 +++++++++++++++---- 3 files changed, 57 insertions(+), 13 deletions(-)